149 lines
6.2 KiB
Scala
149 lines
6.2 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util._
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import freechips.rocketchip.util.property._
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import scala.math.max
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class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Parameters) extends LazyModule
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{
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private def fifoMap(seq: Seq[TLManagerParameters]) = {
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val (flatManagers, keepManagers) = seq.partition(policy)
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// We need to be careful if one flatManager and one keepManager share an existing domain
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// Erring on the side of caution, we will also flatten the keepManager in this case
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val flatDomains = Set(flatManagers.flatMap(_.fifoId):_*) // => ID 0
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val keepDomains = Set(keepManagers.flatMap(_.fifoId):_*) -- flatDomains // => IDs compacted
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// Calculate what the FIFO domains look like after the fixer is applied
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val flatMap = flatDomains.map { x => (x, 0) }.toMap
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val keepMap = keepDomains.scanLeft((-1,0)) { case ((_,s),x) => (x, s+1) }.toMap
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val map = flatMap ++ keepMap
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val fixMap = seq.map { m => m.fifoId match {
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case None => if (policy(m)) Some(0) else None
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case Some(id) => Some(map(id)) // also flattens some who did not ask
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} }
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// Compress the FIFO domain space of those we are combining
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val reMap = flatDomains.scanLeft((-1,-1)) { case ((_,s),x) => (x, s+1) }.toMap
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val splatMap = seq.map { m => m.fifoId match {
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case None => None
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case Some(id) => reMap.lift(id)
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} }
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(fixMap, splatMap)
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}
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val node = TLAdapterNode(
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clientFn = { cp => cp },
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managerFn = { mp =>
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val (fixMap, _) = fifoMap(mp.managers)
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mp.copy(managers = (fixMap zip mp.managers) map { case (id, m) => m.copy(fifoId = id) })
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})
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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val (fixMap, splatMap) = fifoMap(edgeOut.manager.managers)
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// Do we need to serialize the request to this manager?
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val a_notFIFO = edgeIn.manager.fastProperty(in.a.bits.address, _.fifoId != Some(0), (b:Boolean) => Bool(b))
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// Compact the IDs of the cases we serialize
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val compacted = ((fixMap zip splatMap) zip edgeOut.manager.managers) flatMap {
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case ((f, s), m) => if (f == Some(0)) Some(m.copy(fifoId = s)) else None
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}
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val a_id = if (compacted.isEmpty) UInt(0) else
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edgeOut.manager.copy(managers = compacted).findFifoIdFast(in.a.bits.address)
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val a_noDomain = a_id === UInt(0)
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if (false) {
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println(s"FIFOFixer for: ${edgeIn.client.clients.map(_.name).mkString(", ")}")
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println(s"make FIFO: ${edgeIn.manager.managers.filter(_.fifoId==Some(0)).map(_.name).mkString(", ")}")
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println(s"not FIFO: ${edgeIn.manager.managers.filter(_.fifoId!=Some(0)).map(_.name).mkString(", ")}")
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println(s"domains: ${compacted.groupBy(_.name).mapValues(_.map(_.fifoId))}")
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println("")
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}
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// Count beats
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val a_first = edgeIn.first(in.a)
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val d_first = edgeOut.first(out.d) && out.d.bits.opcode =/= TLMessages.ReleaseAck
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// Keep one bit for each source recording if there is an outstanding request that must be made FIFO
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// Sources unused in the stall signal calculation should be pruned by DCE
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val flight = RegInit(Vec.fill(edgeIn.client.endSourceId) { Bool(false) })
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when (a_first && in.a.fire()) { flight(in.a.bits.source) := !a_notFIFO }
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when (d_first && in.d.fire()) { flight(in.d.bits.source) := Bool(false) }
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val stalls = edgeIn.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).map { c =>
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val a_sel = c.sourceId.contains(in.a.bits.source)
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val id = RegEnable(a_id, in.a.fire() && a_sel && !a_notFIFO)
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val track = flight.slice(c.sourceId.start, c.sourceId.end)
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a_sel && a_first && track.reduce(_ || _) && (a_noDomain || id =/= a_id)
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}
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val stall = stalls.foldLeft(Bool(false))(_||_)
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out.a <> in.a
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in.d <> out.d
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out.a.valid := in.a.valid && (a_notFIFO || !stall)
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in.a.ready := out.a.ready && (a_notFIFO || !stall)
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if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
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in .b <> out.b
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out.c <> in .c
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out.e <> in .e
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} else {
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.e.ready := Bool(true)
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out.b.ready := Bool(true)
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out.c.valid := Bool(false)
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out.e.valid := Bool(false)
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}
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//Functional cover properties
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cover(in.a.valid && stall, "COVER FIFOFIXER STALL", "Cover: Stall occured for a valid transaction")
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val SourceIdFIFOed = RegInit(UInt(0, width = edgeIn.client.endSourceId))
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val SourceIdSet = Wire(init = UInt(0, width = edgeIn.client.endSourceId))
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val SourceIdClear = Wire(init = UInt(0, width = edgeIn.client.endSourceId))
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when (a_first && in.a.fire() && !a_notFIFO) {
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SourceIdSet := UIntToOH(in.a.bits.source)
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}
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when (d_first && in.d.fire()) {
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SourceIdClear := UIntToOH(in.d.bits.source)
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}
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SourceIdFIFOed := SourceIdFIFOed | SourceIdSet
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val allIDs_FIFOed = SourceIdFIFOed===Fill(SourceIdFIFOed.getWidth, 1.U)
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cover(allIDs_FIFOed, "COVER all sources", "Cover: FIFOFIXER covers all Source IDs")
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//cover(flight.reduce(_ && _), "COVER full", "Cover: FIFO is full with all Source IDs")
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cover(!(flight.reduce(_ || _)), "COVER empty", "Cover: FIFO is empty")
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cover(SourceIdSet > 0.U, "COVER at least one push", "Cover: At least one Source ID is pushed")
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cover(SourceIdClear > 0.U, "COVER at least one pop", "Cover: At least one Source ID is popped")
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}
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}
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}
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object TLFIFOFixer
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{
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// Which slaves should have their FIFOness combined?
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// NOTE: this transformation is still only applied for masters with requestFifo
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type Policy = TLManagerParameters => Boolean
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import RegionType._
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val all: Policy = m => true
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val allFIFO: Policy = m => m.fifoId.isDefined
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val allUncacheable: Policy = m => m.regionType <= UNCACHEABLE
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def apply(policy: Policy = all)(implicit p: Parameters): TLNode =
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{
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val fixer = LazyModule(new TLFIFOFixer(policy))
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fixer.node
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}
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}
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