64 lines
2.0 KiB
Scala
64 lines
2.0 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import TLMessages._
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import TLPermissions._
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class Atomics(params: TLBundleParameters) extends Module
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{
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val io = new Bundle {
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val write = Bool().flip // ignore opcode
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val a = new TLBundleA(params).flip
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val data_in = UInt(width = params.dataBits).flip
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val data_out = UInt(width = params.dataBits)
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}
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// Arithmetic, what to do
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val adder = io.a.param(2)
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val unsigned = io.a.param(1)
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val take_max = io.a.param(0)
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val signBit = io.a.mask & Cat(UInt(1), ~io.a.mask >> 1)
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val inv_d = Mux(adder, io.data_in, ~io.data_in)
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val sum = (FillInterleaved(8, io.a.mask) & io.a.data) + inv_d
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def sign(x: UInt): Bool = (Cat(x.toBools.grouped(8).map(_.last).toList.reverse) & signBit).orR()
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val sign_a = sign(io.a.data)
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val sign_d = sign(io.data_in)
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val sign_s = sign(sum)
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val a_bigger_uneq = unsigned === sign_a // result if high bits are unequal
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val a_bigger = Mux(sign_a === sign_d, !sign_s, a_bigger_uneq)
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val pick_a = take_max === a_bigger
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// Logical, what to do
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val lut = Vec(Seq(
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UInt(0x6), // XOR
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UInt(0xe), // OR
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UInt(0x8), // AND
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UInt(0xc)))( // SWAP
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io.a.param(1,0))
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val logical = Cat((io.a.data.toBools zip io.data_in.toBools).map { case (a, d) =>
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lut(Cat(a, d))
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}.reverse)
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// Operation, what to do? (0=d, 1=a, 2=sum, 3=logical)
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val select = Mux(io.write, UInt(1), Vec(Seq(
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UInt(1), // PutFullData
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UInt(1), // PutPartialData
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Mux(adder, UInt(2), Mux(pick_a, UInt(1), UInt(0))), // ArithmeticData
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UInt(3), // LogicalData
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UInt(0), // Get
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UInt(0), // Hint
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UInt(0), // AcquireBlock
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UInt(0)))( // AcquirePerm
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io.a.opcode))
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// Only the masked bytes can be modified
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val selects = io.a.mask.toBools.map(b => Mux(b, select, UInt(0)))
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io.data_out := Cat(selects.zipWithIndex.map { case (s, i) =>
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Vec(Seq(io.data_in, io.a.data, sum, logical).map(_((i + 1) * 8 - 1, i * 8)))(s)
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}.reverse)
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}
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