123 lines
4.4 KiB
Scala
123 lines
4.4 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util._
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object TLArbiter
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{
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// (valids, select) => readys
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type Policy = (Integer, UInt, Bool) => UInt
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val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0)
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val roundRobin: Policy = (width, valids, select) => if (width == 1) UInt(1, width=1) else {
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val valid = valids(width-1, 0)
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assert (valid === valids)
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val mask = RegInit(~UInt(0, width=width))
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val filter = Cat(valid & ~mask, valid)
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val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width)
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val readys = ~((unready >> width) & unready(width-1, 0))
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when (select && valid.orR) {
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mask := leftOR(readys & valid, width)
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}
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readys(width-1, 0)
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}
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def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]) {
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apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*)
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}
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def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*) {
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apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
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}
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def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*) {
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apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
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}
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def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*) {
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if (sources.isEmpty) {
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sink.valid := Bool(false)
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} else {
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val pairs = sources.toList
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val beatsIn = pairs.map(_._1)
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val sourcesIn = pairs.map(_._2)
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// The number of beats which remain to be sent
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val beatsLeft = RegInit(UInt(0))
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val idle = beatsLeft === UInt(0)
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val latch = idle && sink.ready // winner (if any) claims sink
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// Who wants access to the sink?
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val valids = sourcesIn.map(_.valid)
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// Arbitrate amongst the requests
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val readys = Vec(policy(valids.size, Cat(valids.reverse), latch).toBools)
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// Which request wins arbitration?
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val winner = Vec((readys zip valids) map { case (r,v) => r&&v })
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// Confirm the policy works properly
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require (readys.size == valids.size)
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// Never two winners
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val prefixOR = winner.scanLeft(Bool(false))(_||_).init
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assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})
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// If there was any request, there is a winner
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assert (!valids.reduce(_||_) || winner.reduce(_||_))
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// Track remaining beats
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val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, UInt(0)) }
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val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats
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beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire())
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// The one-hot source granted access in the previous cycle
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val state = RegInit(Vec.fill(sources.size)(Bool(false)))
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val muxState = Mux(idle, winner, state)
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state := muxState
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if (sources.size > 1) {
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val allowed = Mux(idle, readys, state)
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(sourcesIn zip allowed) foreach { case (s, r) =>
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s.ready := sink.ready && r
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}
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} else {
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sourcesIn(0).ready := sink.ready
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}
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sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids))
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sink.bits := Mux1H(muxState, sourcesIn.map(_.bits))
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}
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}
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}
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/** Synthesizeable unit tests */
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import freechips.rocketchip.unittest._
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class TestRobin(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
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val sources = Wire(Vec(6, DecoupledIO(UInt(width=3))))
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val sink = Wire(DecoupledIO(UInt(width=3)))
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val count = RegInit(UInt(0, width=8))
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val lfsr = LFSR16(Bool(true))
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val valid = lfsr(0)
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val ready = lfsr(15)
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sources.zipWithIndex.map { case (z, i) => z.bits := UInt(i) }
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sources(0).valid := valid
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sources(1).valid := Bool(false)
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sources(2).valid := valid
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sources(3).valid := valid
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sources(4).valid := Bool(false)
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sources(5).valid := valid
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sink.ready := ready
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TLArbiter(TLArbiter.roundRobin)(sink, sources.zipWithIndex.map { case (z, i) => (UInt(i), z) }:_*)
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when (sink.fire()) { printf("TestRobin: %d\n", sink.bits) }
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when (!sink.fire()) { printf("TestRobin: idle (%d %d)\n", valid, ready) }
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count := count + UInt(1)
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io.finished := count >= UInt(txns)
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}
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