103 lines
3.1 KiB
Scala
103 lines
3.1 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tile
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import Chisel._
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import freechips.rocketchip.config._
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import freechips.rocketchip.rocket._
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import freechips.rocketchip.util._
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case object BuildCore extends Field[Parameters => CoreModule with HasCoreIO]
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case object XLen extends Field[Int]
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// These parameters can be varied per-core
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trait CoreParams {
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val bootFreqHz: BigInt
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val useVM: Boolean
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val useUser: Boolean
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val useDebug: Boolean
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val useAtomics: Boolean
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val useAtomicsOnlyForIO: Boolean
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val useCompressed: Boolean
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val mulDiv: Option[MulDivParams]
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val fpu: Option[FPUParams]
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val fetchWidth: Int
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val decodeWidth: Int
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val retireWidth: Int
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val instBits: Int
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val nLocalInterrupts: Int
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val nPMPs: Int
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val nBreakpoints: Int
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val nPerfCounters: Int
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val haveBasicCounters: Boolean
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val misaWritable: Boolean
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val nL2TLBEntries: Int
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val mtvecInit: Option[BigInt]
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val mtvecWritable: Boolean
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val tileControlAddr: Option[BigInt]
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def instBytes: Int = instBits / 8
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def fetchBytes: Int = fetchWidth * instBytes
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}
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trait HasCoreParameters extends HasTileParameters {
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val coreParams: CoreParams = tileParams.core
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val fLen = coreParams.fpu.map(_.fLen).getOrElse(0)
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val usingMulDiv = coreParams.mulDiv.nonEmpty
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val usingFPU = coreParams.fpu.nonEmpty
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val usingAtomics = coreParams.useAtomics
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val usingAtomicsOnlyForIO = coreParams.useAtomicsOnlyForIO
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val usingAtomicsInCache = usingAtomics && !usingAtomicsOnlyForIO
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val usingCompressed = coreParams.useCompressed
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val retireWidth = coreParams.retireWidth
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val fetchWidth = coreParams.fetchWidth
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val decodeWidth = coreParams.decodeWidth
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val fetchBytes = coreParams.fetchBytes
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val coreInstBits = coreParams.instBits
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val coreInstBytes = coreInstBits/8
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val coreDataBits = xLen max fLen
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val coreDataBytes = coreDataBits/8
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val coreMaxAddrBits = paddrBits max vaddrBitsExtended
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val nBreakpoints = coreParams.nBreakpoints
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val nPMPs = coreParams.nPMPs
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val nPerfCounters = coreParams.nPerfCounters
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val mtvecInit = coreParams.mtvecInit
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val mtvecWritable = coreParams.mtvecWritable
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val coreDCacheReqTagBits = 6
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val dcacheReqTagBits = coreDCacheReqTagBits + log2Ceil(dcacheArbPorts)
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// Print out log of committed instructions and their writeback values.
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// Requires post-processing due to out-of-order writebacks.
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val enableCommitLog = false
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}
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abstract class CoreModule(implicit val p: Parameters) extends Module
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with HasCoreParameters
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abstract class CoreBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasCoreParameters
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class CoreInterrupts(implicit p: Parameters) extends TileInterrupts()(p) {
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val buserror = coreParams.tileControlAddr.map(a => Bool())
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}
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trait HasCoreIO extends HasTileParameters {
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implicit val p: Parameters
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val io = new CoreBundle()(p) with HasExternallyDrivenTileConstants {
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val interrupts = new CoreInterrupts().asInput
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val imem = new FrontendIO
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val dmem = new HellaCacheIO
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val ptw = new DatapathPTWIO().flip
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val fpu = new FPUCoreIO().flip
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val rocc = new RoCCCoreIO().flip
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val trace = Vec(coreParams.retireWidth, new TracedInstruction).asOutput
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}
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}
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