200 lines
8.6 KiB
Scala
200 lines
8.6 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.regmapper
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import Chisel._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util.{GenericParameterizedBundle, ReduceOthers}
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import freechips.rocketchip.util.property._
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import chisel3.internal.sourceinfo.{SourceInfo, SourceLine}
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// A bus agnostic register interface to a register-based device
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case class RegMapperParams(indexBits: Int, maskBits: Int, extraBits: Int)
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class RegMapperInput(params: RegMapperParams) extends GenericParameterizedBundle(params)
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{
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val read = Bool()
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val index = UInt(width = params.indexBits)
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val data = UInt(width = params.maskBits*8)
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val mask = UInt(width = params.maskBits)
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val extra = UInt(width = params.extraBits)
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}
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class RegMapperOutput(params: RegMapperParams) extends GenericParameterizedBundle(params)
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{
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val read = Bool()
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val data = UInt(width = params.maskBits*8)
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val extra = UInt(width = params.extraBits)
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}
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object RegMapper
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{
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// Create a generic register-based device
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def apply(bytes: Int, concurrency: Int, undefZero: Boolean, in: DecoupledIO[RegMapperInput], mapping: RegField.Map*)(implicit sourceInfo: SourceInfo) = {
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val bytemap = mapping.toList
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// Negative addresses are bad
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bytemap.foreach { byte => require (byte._1 >= 0) }
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// Transform all fields into bit offsets Seq[(bit, field)]
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val bitmap = bytemap.map { case (byte, fields) =>
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val bits = fields.scanLeft(byte * 8)(_ + _.width).init
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bits zip fields
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}.flatten.sortBy(_._1)
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// Detect overlaps
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(bitmap.init zip bitmap.tail) foreach { case ((lbit, lfield), (rbit, rfield)) =>
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require (lbit + lfield.width <= rbit, s"Register map overlaps at bit ${rbit}.")
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}
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// Group those fields into bus words Map[word, List[(bit, field)]]
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val wordmap = bitmap.groupBy(_._1 / (8*bytes))
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// Make sure registers fit
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val inParams = in.bits.params
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val inBits = inParams.indexBits
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assert (wordmap.keySet.max < (1 << inBits), "Register map does not fit in device")
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val out = Wire(Decoupled(new RegMapperOutput(inParams)))
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val front = Wire(Decoupled(new RegMapperInput(inParams)))
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front.bits := in.bits
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// Must this device pipeline the control channel?
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val pipelined = wordmap.values.map(_.map(_._2.pipelined)).flatten.reduce(_ || _)
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val depth = concurrency
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require (depth >= 0)
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require (!pipelined || depth > 0, "Register-based device with request/response handshaking needs concurrency > 0")
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val back = if (depth > 0) Queue(front, depth) else front
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// Convert to and from Bits
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def toBits(x: Int, tail: List[Boolean] = List.empty): List[Boolean] =
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if (x == 0) tail.reverse else toBits(x >> 1, ((x & 1) == 1) :: tail)
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def ofBits(bits: List[Boolean]) = bits.foldRight(0){ case (x,y) => (if (x) 1 else 0) | y << 1 }
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// Find the minimal mask that can decide the register map
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val mask = AddressDecoder(wordmap.keySet.toList)
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val maskMatch = ~UInt(mask, width = inBits)
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val maskFilter = toBits(mask)
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val maskBits = maskFilter.filter(x => x).size
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// Calculate size and indexes into the register map
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val regSize = 1 << maskBits
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def regIndexI(x: Int) = ofBits((maskFilter zip toBits(x)).filter(_._1).map(_._2))
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def regIndexU(x: UInt) = if (maskBits == 0) UInt(0) else
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Cat((maskFilter zip x.toBools).filter(_._1).map(_._2).reverse)
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// Protection flag for undefined registers
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val iRightReg = Array.fill(regSize) { Bool(true) }
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val oRightReg = Array.fill(regSize) { Bool(true) }
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// Transform the wordmap into minimal decoded indexes, Seq[(index, bit, field)]
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val flat = wordmap.toList.map { case (word, fields) =>
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val index = regIndexI(word)
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val uint = UInt(word, width = inBits)
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if (undefZero) {
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iRightReg(index) = ((front.bits.index ^ uint) & maskMatch) === UInt(0)
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oRightReg(index) = ((back .bits.index ^ uint) & maskMatch) === UInt(0)
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}
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// Confirm that no field spans a word boundary
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fields foreach { case (bit, field) =>
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val off = bit - 8*bytes*word
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// println(s"Reg ${word}: [${off}, ${off+field.width})")
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require (off + field.width <= bytes * 8, s"Field at word ${word}*(${bytes}B) has bits [${off}, ${off+field.width}), which exceeds word limit.")
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}
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// println("mapping 0x%x -> 0x%x for 0x%x/%d".format(word, index, mask, maskBits))
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fields.map { case (bit, field) => (index, bit-8*bytes*word, field) }
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}.flatten
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// Forward declaration of all flow control signals
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val rivalid = Wire(Vec(flat.size, Bool()))
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val wivalid = Wire(Vec(flat.size, Bool()))
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val roready = Wire(Vec(flat.size, Bool()))
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val woready = Wire(Vec(flat.size, Bool()))
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// Per-register list of all control signals needed for data to flow
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val rifire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }
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val wifire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }
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val rofire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }
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val wofire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }
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// The output values for each register
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val dataOut = Array.tabulate(regSize) { _ => UInt(0) }
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// Which bits are touched?
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val frontMask = FillInterleaved(8, front.bits.mask)
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val backMask = FillInterleaved(8, back .bits.mask)
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// Connect the fields
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for (i <- 0 until flat.size) {
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val (reg, low, field) = flat(i)
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val high = low + field.width - 1
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// Confirm that no register is too big
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require (high < 8*bytes)
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val rimask = frontMask(high, low).orR()
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val wimask = frontMask(high, low).andR()
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val romask = backMask(high, low).orR()
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val womask = backMask(high, low).andR()
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val data = if (field.write.combinational) back.bits.data else front.bits.data
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val f_rivalid = rivalid(i) && rimask
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val f_roready = roready(i) && romask
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val f_wivalid = wivalid(i) && wimask
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val f_woready = woready(i) && womask
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val (f_riready, f_rovalid, f_data) = field.read.fn(f_rivalid, f_roready)
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val (f_wiready, f_wovalid) = field.write.fn(f_wivalid, f_woready, data(high, low))
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// cover reads and writes to register
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val fname = field.desc.map{_.name}.getOrElse("")
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val fdesc = field.desc.map{_.desc + ":"}.getOrElse("")
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cover(f_rivalid && f_riready, fname + "_Reg_read_start", fdesc + " RegField Read Request Initiate")
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cover(f_rovalid && f_roready, fname + "_Reg_read_out", fdesc + " RegField Read Request Complete")
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cover(f_wivalid && f_wiready, fname + "_Reg_write_start", fdesc + " RegField Write Request Initiate")
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cover(f_wovalid && f_woready, fname + "_Reg_write_out", fdesc + " RegField Write Request Complete")
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def litOR(x: Bool, y: Bool) = if (x.isLit && x.litValue == 1) Bool(true) else x || y
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// Add this field to the ready-valid signals for the register
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rifire(reg) = (rivalid(i), litOR(f_riready, !rimask)) +: rifire(reg)
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wifire(reg) = (wivalid(i), litOR(f_wiready, !wimask)) +: wifire(reg)
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rofire(reg) = (roready(i), litOR(f_rovalid, !romask)) +: rofire(reg)
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wofire(reg) = (woready(i), litOR(f_wovalid, !womask)) +: wofire(reg)
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dataOut(reg) = dataOut(reg) | ((f_data << low) & (~UInt(0, width = high+1)))
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}
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// Which register is touched?
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val iindex = regIndexU(front.bits.index)
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val oindex = regIndexU(back .bits.index)
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val frontSel = UIntToOH(iindex).toBools
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val backSel = UIntToOH(oindex).toBools
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// Compute: is the selected register ready? ... and cross-connect all ready-valids
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def mux(valid: Bool, select: Seq[Bool], guard: Seq[Bool], flow: Seq[Seq[(Bool, Bool)]]): Vec[Bool] =
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Vec(((select zip guard) zip flow).map { case ((s, g), f) =>
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val out = Wire(Bool())
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ReduceOthers((out, valid && s && g) +: f)
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out || !g
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})
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// Include the per-register one-hot selected criteria
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val rifireMux = mux(in.valid && front.ready && front.bits.read, frontSel, iRightReg, rifire)
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val wifireMux = mux(in.valid && front.ready && !front.bits.read, frontSel, iRightReg, wifire)
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val rofireMux = mux(back.valid && out.ready && back .bits.read, backSel, oRightReg, rofire)
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val wofireMux = mux(back.valid && out.ready && !back .bits.read, backSel, oRightReg, wofire)
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val iready = Mux(front.bits.read, rifireMux(iindex), wifireMux(iindex))
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val oready = Mux(back .bits.read, rofireMux(oindex), wofireMux(oindex))
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// Connect the pipeline
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in.ready := front.ready && iready
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front.valid := in.valid && iready
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back.ready := out.ready && oready
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out.valid := back.valid && oready
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out.bits.read := back.bits.read
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out.bits.data := Mux(Vec(oRightReg)(oindex), Vec(dataOut)(oindex), UInt(0))
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out.bits.extra := back.bits.extra
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out
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}
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}
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