71 lines
1.8 KiB
Scala
71 lines
1.8 KiB
Scala
// See LICENSE.jtag for license details.
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package freechips.rocketchip.jtag
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import Chisel._
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import chisel3.core.{Input, Output}
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import chisel3.experimental.withClock
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/** Bundle representing a tristate pin.
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*/
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class Tristate extends Bundle {
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val data = Bool()
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val driven = Bool() // active high, pin is hi-Z when driven is low
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}
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/** Generates a register that updates on the falling edge of the input clock signal.
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*/
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object NegEdgeReg {
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def apply[T <: Data](clock: Clock, next: T, enable: Bool=true.B, name: Option[String] = None): T = {
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// TODO pass in initial value as well
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withClock((!clock.asUInt).asClock) {
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val reg = RegEnable(next = next, enable = enable)
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name.foreach{reg.suggestName(_)}
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reg
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}
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}
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}
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/** A module that counts transitions on the input clock line, used as a basic sanity check and
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* debug indicator clock-crossing designs.
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*/
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class ClockedCounter(counts: BigInt, init: Option[BigInt]) extends Module {
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require(counts > 0, "really?")
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val width = log2Ceil(counts)
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class CountIO extends Bundle {
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val count = Output(UInt(width.W))
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}
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val io = IO(new CountIO)
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val count = init match {
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case Some(init) => RegInit(init.U(width.W))
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case None => Reg(UInt(width.W))
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}
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when (count === (counts - 1).asUInt) {
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count := 0.U
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} .otherwise {
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count := count + 1.U
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}
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io.count := count
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}
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/** Count transitions on the input bit by specifying it as a clock to a counter.
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*/
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object ClockedCounter {
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def apply (data: Bool, counts: BigInt, init: BigInt): UInt = {
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withClock(data.asClock) {
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val counter = Module(new ClockedCounter(counts, Some(init)))
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counter.io.count
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}
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}
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def apply (data: Bool, counts: BigInt): UInt = {
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withClock(data.asClock) {
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val counter = Module(new ClockedCounter(counts, None))
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counter.io.count
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}
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}
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}
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