62 lines
1.9 KiB
Scala
62 lines
1.9 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.interrupts
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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// A potentially empty half-open range; [start, end)
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case class IntRange(start: Int, end: Int)
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{
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require (start >= 0)
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require (start <= end)
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def size = end - start
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def overlaps(x: IntRange) = start < x.end && x.start < end
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def offset(x: Int) = IntRange(x+start, x+end)
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}
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object IntRange
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{
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implicit def apply(end: Int): IntRange = apply(0, end)
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}
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case class IntSourceParameters(
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range: IntRange,
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resources: Seq[Resource] = Seq(),
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nodePath: Seq[BaseNode] = Seq())
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{
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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}
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case class IntSinkParameters(
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nodePath: Seq[BaseNode] = Seq())
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{
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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}
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case class IntSourcePortParameters(sources: Seq[IntSourceParameters])
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{
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val num = sources.map(_.range.size).sum
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// The interrupts mapping must not overlap
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sources.map(_.range).combinations(2).foreach { case Seq(a, b) => require (!a.overlaps(b)) }
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// The interrupts must perfectly cover the range
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require (sources.isEmpty || sources.map(_.range.end).max == num)
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}
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object IntSourcePortSimple
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{
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def apply(num: Int = 1, ports: Int = 1, sources: Int = 1, resources: Seq[Resource] = Nil) =
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if (num == 0) Nil else
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Seq.fill(ports)(IntSourcePortParameters(Seq.fill(sources)(IntSourceParameters(range = IntRange(0, num), resources = resources))))
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}
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case class IntSinkPortParameters(sinks: Seq[IntSinkParameters])
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object IntSinkPortSimple
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{
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def apply(ports: Int = 1, sinks: Int = 1) =
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Seq.fill(ports)(IntSinkPortParameters(Seq.fill(sinks)(IntSinkParameters())))
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}
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case class IntEdge(source: IntSourcePortParameters, sink: IntSinkPortParameters, params: Parameters, sourceInfo: SourceInfo)
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