68 lines
3.6 KiB
Scala
68 lines
3.6 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.interrupts
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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object IntImp extends SimpleNodeImp[IntSourcePortParameters, IntSinkPortParameters, IntEdge, Vec[Bool]]
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{
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def edge(pd: IntSourcePortParameters, pu: IntSinkPortParameters, p: Parameters, sourceInfo: SourceInfo) = IntEdge(pd, pu, p, sourceInfo)
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def bundle(e: IntEdge) = Vec(e.source.num, Bool())
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def render(e: IntEdge) = RenderedEdge(colour = "#0000ff" /* blue */, label = e.source.sources.map(_.range.size).sum.toString, flipped = true)
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override def mixO(pd: IntSourcePortParameters, node: OutwardNode[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]): IntSourcePortParameters =
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pd.copy(sources = pd.sources.map { s => s.copy (nodePath = node +: s.nodePath) })
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override def mixI(pu: IntSinkPortParameters, node: InwardNode[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]): IntSinkPortParameters =
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pu.copy(sinks = pu.sinks.map { s => s.copy (nodePath = node +: s.nodePath) })
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}
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case class IntSourceNode(portParams: Seq[IntSourcePortParameters])(implicit valName: ValName) extends SourceNode(IntImp)(portParams)
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case class IntSinkNode(portParams: Seq[IntSinkPortParameters])(implicit valName: ValName) extends SinkNode(IntImp)(portParams)
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case class IntAdapterNode(
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sourceFn: IntSourcePortParameters => IntSourcePortParameters = { s => s },
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sinkFn: IntSinkPortParameters => IntSinkPortParameters = { s => s })(
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implicit valName: ValName)
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extends AdapterNode(IntImp)(sourceFn, sinkFn)
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case class IntIdentityNode()(implicit valName: ValName) extends IdentityNode(IntImp)()
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case class IntNexusNode(
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sourceFn: Seq[IntSourcePortParameters] => IntSourcePortParameters,
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sinkFn: Seq[IntSinkPortParameters] => IntSinkPortParameters,
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inputRequiresOutput: Boolean = true,
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outputRequiresInput: Boolean = true)(
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implicit valName: ValName)
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extends NexusNode(IntImp)(sourceFn, sinkFn, inputRequiresOutput, outputRequiresInput)
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object IntSyncImp extends SimpleNodeImp[IntSourcePortParameters, IntSinkPortParameters, IntEdge, SyncInterrupts]
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{
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def edge(pd: IntSourcePortParameters, pu: IntSinkPortParameters, p: Parameters, sourceInfo: SourceInfo) = IntEdge(pd, pu, p, sourceInfo)
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def bundle(e: IntEdge) = new SyncInterrupts(e)
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def render(e: IntEdge) = RenderedEdge(colour = "#ff00ff" /* purple */, label = e.source.sources.map(_.range.size).sum.toString, flipped = true)
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override def mixO(pd: IntSourcePortParameters, node: OutwardNode[IntSourcePortParameters, IntSinkPortParameters, SyncInterrupts]): IntSourcePortParameters =
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pd.copy(sources = pd.sources.map { s => s.copy (nodePath = node +: s.nodePath) })
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override def mixI(pu: IntSinkPortParameters, node: InwardNode[IntSourcePortParameters, IntSinkPortParameters, SyncInterrupts]): IntSinkPortParameters =
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pu.copy(sinks = pu.sinks.map { s => s.copy (nodePath = node +: s.nodePath) })
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}
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case class IntSyncIdentityNode()(implicit valName: ValName) extends IdentityNode(IntSyncImp)()
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case class IntSyncSourceNode(alreadyRegistered: Boolean)(implicit valName: ValName)
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extends MixedAdapterNode(IntImp, IntSyncImp)(
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dFn = { p => p },
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uFn = { p => p })
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{
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override lazy val nodedebugstring = s"alreadyRegistered:${alreadyRegistered}"
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}
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case class IntSyncSinkNode(sync: Int)(implicit valName: ValName)
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extends MixedAdapterNode(IntSyncImp, IntImp)(
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dFn = { p => p },
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uFn = { p => p })
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{
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override lazy val nodedebugstring = s"sync:${sync}"
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}
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