67 lines
1.7 KiB
Scala
67 lines
1.7 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.interrupts
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
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import freechips.rocketchip.diplomacy._
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@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
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class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
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{
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val intnode = IntAdapterNode()
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lazy val module = new LazyModuleImp(this) {
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(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
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out := SynchronizerShiftReg(in, sync)
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}
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}
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}
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object IntSyncCrossingSource
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{
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def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
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{
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val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
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intsource.node
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}
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}
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class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
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{
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val node = IntSyncSourceNode(alreadyRegistered)
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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if (alreadyRegistered) {
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out.sync := in
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} else {
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out.sync := AsyncResetReg(Cat(in.reverse)).toBools
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}
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}
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}
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}
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class IntSyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
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{
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val node = IntSyncSinkNode(sync)
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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out := SynchronizerShiftReg(in.sync, sync)
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}
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}
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}
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object IntSyncCrossingSink
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{
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def apply(sync: Int = 3)(implicit p: Parameters) =
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{
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val intsink = LazyModule(new IntSyncCrossingSink(sync))
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intsink.node
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}
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}
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