604 lines
18 KiB
Scala
604 lines
18 KiB
Scala
// See LICENSE.Berkeley for license details.
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// See LICENSE.SiFive for license details.
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// This file was originally written by Matthew Naylor, University of
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// Cambridge, based on code already present in the groundtest repo.
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//
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// This software was partly developed by the University of Cambridge
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// Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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// ("CTSRD"), as part of the DARPA CRASH research programme.
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//
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// This software was partly developed by the University of Cambridge
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// Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249
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// ("MRC2"), as part of the DARPA MRC research programme.
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//
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// This software was partly developed by the University of Cambridge
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// Computer Laboratory as part of the Rigorous Engineering of
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// Mainstream Systems (REMS) project, funded by EPSRC grant
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// EP/K008528/1.
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package freechips.rocketchip.groundtest
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.rocket._
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import freechips.rocketchip.tile._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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import scala.util.Random
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// =======
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// Outline
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// =======
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// Generate memory traces that result from random sequences of memory
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// operations. These traces can then be validated by an external
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// tool. A trace is a simply sequence of memory requests and
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// responses.
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// ==========================
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// Trace-generator parameters
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// ==========================
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// Compile-time parameters:
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//
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// * The id of the generator (there may be more than one in a
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// multi-core system).
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//
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// * The total number of generators present in the system.
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//
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// * The desired number of requests to be sent by each generator.
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//
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// * A bag of physical addresses, shared by all cores, from which an
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// address can be drawn when generating a fresh request.
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//
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// * A number of random 'extra addresses', local to each core, from
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// which an address can be drawn when generating a fresh request.
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// (This is a way to generate a wider range of addresses without having
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// to repeatedly recompile with a different address bag.)
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case class TraceGenParams(
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dcache: Option[DCacheParams] = Some(DCacheParams()),
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wordBits: Int, // p(XLen)
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addrBits: Int, // p(PAddrBits)
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addrBag: List[BigInt], // p(AddressBag)
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maxRequests: Int,
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memStart: BigInt, //p(ExtMem).base
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numGens: Int) extends GroundTestTileParams {
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def build(i: Int, p: Parameters): GroundTestTile = new TraceGenTile(i, this)(p)
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val hartId = 0
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val trace = false
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val blockerCtrlAddr = None
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}
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trait HasTraceGenParams {
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implicit val p: Parameters
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val params: TraceGenParams
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val pAddrBits = params.addrBits
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val numGens = params.numGens
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val numReqsPerGen = params.maxRequests
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val memStart = params.memStart
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val memRespTimeout = 8192
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val numBitsInWord = params.wordBits
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val numBytesInWord = numBitsInWord / 8
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val numBitsInWordOffset = log2Up(numBytesInWord)
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val addressBag = params.addrBag
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val addressBagLen = addressBag.length
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val logAddressBagLen = log2Up(addressBagLen)
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val genExtraAddrs = false
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val logNumExtraAddrs = 1
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val numExtraAddrs = 1 << logNumExtraAddrs
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val maxTags = 8
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require(numBytesInWord * 8 == numBitsInWord)
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require((1 << logAddressBagLen) == addressBagLen)
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}
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// ============
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// Trace format
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// ============
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// Let <id> denote a generator id;
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// <addr> denote an address (in hex);
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// <data> denote a value that is stored at an address;
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// <tag> denote a unique request/response id;
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// and <time> denote an integer representing a cycle-count.
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// Each line in the trace takes one of the following formats.
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//
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// <id>: load-req <addr> #<tag> @<time>
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// <id>: load-reserve-req <addr> #<tag> @<time>
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// <id>: store-req <data> <addr> #<tag> @<time>
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// <id>: store-cond-req <data> <addr> #<tag> @<time>
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// <id>: swap-req <data> <addr> #<tag> @<time>
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// <id>: resp <data> #<tag> @<time>
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// <id>: fence-req @<time>
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// <id>: fence-resp @<time>
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// NOTE: The (address, value) pair of every generated store is unique,
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// i.e. the same value is never written to the same address twice.
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// This aids trace validation.
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// ============
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// Random seeds
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// ============
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// The generator employs "unitialised registers" to seed its PRNGs;
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// these are randomly initialised by the C++ backend. This means that
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// the "-s" command-line argument to the Rocket emulator can be used
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// to generate new traces, or to replay specific ones.
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// ===========
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// Tag manager
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// ===========
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// This is used to obtain unique tags for memory requests: each
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// request must carry a unique tag since responses can come back
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// out-of-order.
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//
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// The tag manager can be viewed as a set of tags. The user can take
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// a tag out of the set (if there is one available) and later put it
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// back.
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class TagMan(val logNumTags : Int) extends Module {
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val io = new Bundle {
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// Is there a tag available?
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val available = Bool(OUTPUT)
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// If so, which one?
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val tagOut = UInt(OUTPUT, logNumTags)
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// User pulses this to take the currently available tag
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val take = Bool(INPUT)
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// User pulses this to put a tag back
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val put = Bool(INPUT)
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// And the tag put back is
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val tagIn = UInt(INPUT, logNumTags)
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}
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// Total number of tags available
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val numTags = 1 << logNumTags
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// For each tag, record whether or not it is in use
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val inUse = List.fill(numTags)(Reg(init = Bool(false)))
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// Mapping from each tag to its 'inUse' bit
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val inUseMap = (0 to numTags-1).map(i => UInt(i)).zip(inUse)
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// Next tag to offer
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val nextTag = Reg(init = UInt(0, logNumTags))
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io.tagOut := nextTag
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// Is the next tag available?
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io.available := ~MuxLookup(nextTag, Bool(true), inUseMap)
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// When user takes a tag
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when (io.take) {
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for ((i, b) <- inUseMap) {
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when (i === nextTag) { b := Bool(true) }
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}
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nextTag := nextTag + UInt(1)
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}
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// When user puts a tag back
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when (io.put) {
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for ((i, b) <- inUseMap) {
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when (i === io.tagIn) { b := Bool(false) }
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}
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}
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}
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// ===============
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// Trace generator
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// ===============
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class TraceGenerator(val params: TraceGenParams)(implicit val p: Parameters) extends Module
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with HasTraceGenParams {
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val io = new Bundle {
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val finished = Bool(OUTPUT)
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val timeout = Bool(OUTPUT)
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val mem = new HellaCacheIO
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val hartid = UInt(INPUT, log2Up(numGens))
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}
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val totalNumAddrs = addressBag.size + numExtraAddrs
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val initCount = Reg(init = UInt(0, log2Up(totalNumAddrs)))
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val initDone = Reg(init = Bool(false))
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val reqTimer = Module(new Timer(8192, maxTags))
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reqTimer.io.start.valid := io.mem.req.fire()
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reqTimer.io.start.bits := io.mem.req.bits.tag
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reqTimer.io.stop.valid := io.mem.resp.valid
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reqTimer.io.stop.bits := io.mem.resp.bits.tag
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// Random addresses
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// ----------------
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// Address bag, shared by all cores, taken from module parameters.
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// In addition, there is a per-core random selection of extra addresses.
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val bagOfAddrs = addressBag.map(x => UInt(memStart + x, pAddrBits))
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val extraAddrs = Seq.fill(numExtraAddrs) {
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UInt(memStart + Random.nextInt(1 << 16) * numBytesInWord, pAddrBits)
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}
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// A random index into the address bag.
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val randAddrBagIndex = LCG(logAddressBagLen)
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// A random address from the address bag.
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val addrBagIndices = (0 to addressBagLen-1).
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map(i => UInt(i, logAddressBagLen))
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val randAddrFromBag = MuxLookup(randAddrBagIndex, UInt(0),
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addrBagIndices.zip(bagOfAddrs))
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// Random address from the address bag or the extra addresses.
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val extraAddrIndices = (0 to numExtraAddrs-1)
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.map(i => UInt(i, logNumExtraAddrs))
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val randAddr =
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if (! genExtraAddrs) {
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randAddrFromBag
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}
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else {
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// A random index into the extra addresses.
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val randExtraAddrIndex = LCG(logNumExtraAddrs)
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// A random address from the extra addresses.
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val randAddrFromExtra = Cat(UInt(0),
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MuxLookup(randExtraAddrIndex, UInt(0),
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extraAddrIndices.zip(extraAddrs)), UInt(0, 3))
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Frequency(List(
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(1, randAddrFromBag),
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(1, randAddrFromExtra)))
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}
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val allAddrs = extraAddrs ++ bagOfAddrs
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val allAddrIndices = (0 until totalNumAddrs)
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.map(i => UInt(i, log2Ceil(totalNumAddrs)))
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val initAddr = MuxLookup(initCount, UInt(0),
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allAddrIndices.zip(allAddrs))
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// Random opcodes
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// --------------
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// Generate random opcodes for memory operations according to the
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// given frequency distribution.
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// Opcodes
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val (opNop :: opLoad :: opStore ::
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opFence :: opLRSC :: opSwap ::
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opDelay :: Nil) = Enum(Bits(), 7)
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// Distribution specified as a list of (frequency,value) pairs.
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// NOTE: frequencies must sum to a power of two.
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val randOp = Frequency(List(
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(10, opLoad),
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(10, opStore),
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(4, opFence),
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(3, opLRSC),
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(3, opSwap),
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(2, opDelay)))
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// Request/response tags
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// ---------------------
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// Responses may come back out-of-order. Each request and response
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// therefore contains a unique 7-bit identifier, referred to as a
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// "tag", used to match each response with its corresponding request.
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// Create a tag manager giving out unique 3-bit tags
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val tagMan = Module(new TagMan(log2Ceil(maxTags)))
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// Default inputs
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tagMan.io.take := Bool(false);
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tagMan.io.put := Bool(false);
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tagMan.io.tagIn := UInt(0);
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// Cycle counter
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// -------------
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// 32-bit cycle count used to record send-times of requests and
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// receive-times of respones.
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val cycleCount = Reg(init = UInt(0, 32))
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cycleCount := cycleCount + UInt(1);
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// Delay timer
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// -----------
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// Used to implement the delay operation and to insert random
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// delays between load-reserve and store-conditional commands.
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// A 16-bit timer is plenty
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val delayTimer = Module(new DynamicTimer(16))
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// Used to generate a random delay period
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val randDelayBase = LCG16()
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// Random delay period: usually small, occasionally big
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val randDelay = Frequency(List(
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(14, UInt(0, 13) ## randDelayBase(2, 0)),
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(2, UInt(0, 11) ## randDelayBase(5, 0))))
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// Default inputs
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delayTimer.io.start := Bool(false)
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delayTimer.io.period := randDelay
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delayTimer.io.stop := Bool(false)
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// Operation dispatch
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// ------------------
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// Hardware thread id
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val tid = io.hartid
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// Request & response count
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val reqCount = Reg(init = UInt(0, 32))
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val respCount = Reg(init = UInt(0, 32))
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// Current operation being executed
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val currentOp = Reg(init = opNop)
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// If larger than 0, a multi-cycle operation is in progress.
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// Value indicates stage of progress.
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val opInProgress = Reg(init = UInt(0, 2))
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// Indicate when a fresh request is to be sent
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val sendFreshReq = Wire(Bool())
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sendFreshReq := Bool(false)
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// Used to generate unique data values
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val nextData = Reg(init = UInt(1, numBitsInWord-tid.getWidth))
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// Registers for all the interesting parts of a request
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val reqValid = Reg(init = Bool(false))
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val reqAddr = Reg(init = UInt(0, numBitsInWord))
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val reqData = Reg(init = UInt(0, numBitsInWord))
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val reqCmd = Reg(init = UInt(0, 5))
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val reqTag = Reg(init = UInt(0, 7))
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// Condition on being allowed to send a fresh request
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val canSendFreshReq = (!reqValid || io.mem.req.fire()) &&
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tagMan.io.available
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// Operation dispatch
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when (reqCount < UInt(numReqsPerGen)) {
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// No-op
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when (currentOp === opNop) {
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// Move on to a new operation
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currentOp := Mux(initDone, randOp, opStore)
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}
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// Fence
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when (currentOp === opFence) {
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when (opInProgress === UInt(0) && !reqValid) {
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// Emit fence request
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printf("%d: fence-req @%d\n", tid, cycleCount)
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// Multi-cycle operation now in progress
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opInProgress := UInt(1)
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}
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// Wait until all requests have had a response
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.elsewhen (reqCount === respCount) {
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// Emit fence response
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printf("%d: fence-resp @%d\n", tid, cycleCount)
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// Move on to a new operation
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currentOp := randOp
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// Operation finished
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opInProgress := UInt(0)
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}
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}
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// Delay
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when (currentOp === opDelay) {
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when (opInProgress === UInt(0)) {
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// Start timer
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delayTimer.io.start := Bool(true)
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// Multi-cycle operation now in progress
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opInProgress := UInt(1)
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}
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.elsewhen (delayTimer.io.timeout) {
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// Move on to a new operation
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currentOp := randOp
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// Operation finished
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opInProgress := UInt(0)
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}
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}
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// Load, store, or atomic swap
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when (currentOp === opLoad ||
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currentOp === opStore ||
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currentOp === opSwap) {
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when (canSendFreshReq) {
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// Set address
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reqAddr := Mux(initDone, randAddr, initAddr)
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// Set command
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when (currentOp === opLoad) {
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reqCmd := M_XRD
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} .elsewhen (currentOp === opStore) {
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reqCmd := M_XWR
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} .elsewhen (currentOp === opSwap) {
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reqCmd := M_XA_SWAP
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}
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// Send request
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sendFreshReq := Bool(true)
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// Move on to a new operation
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when (!initDone && initCount =/= UInt(totalNumAddrs - 1)) {
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initCount := initCount + UInt(1)
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currentOp := opStore
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} .otherwise {
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currentOp := randOp
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initDone := Bool(true)
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}
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}
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}
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// Load-reserve and store-conditional
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// First issue an LR, then delay, then issue an SC
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when (currentOp === opLRSC) {
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// LR request has not yet been sent
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when (opInProgress === UInt(0)) {
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when (canSendFreshReq) {
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// Set address and command
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reqAddr := randAddr
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reqCmd := M_XLR
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// Send request
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sendFreshReq := Bool(true)
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// Multi-cycle operation now in progress
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opInProgress := UInt(1)
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}
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}
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// LR request has been sent, start delay timer
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when (opInProgress === UInt(1)) {
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// Start timer
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delayTimer.io.start := Bool(true)
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// Indicate that delay has started
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opInProgress := UInt(2)
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}
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// Delay in progress
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when (opInProgress === UInt(2)) {
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when (delayTimer.io.timeout) {
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// Delay finished
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opInProgress := UInt(3)
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}
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}
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// Delay finished, send SC request
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when (opInProgress === UInt(3)) {
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when (canSendFreshReq) {
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// Set command, but leave address
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// i.e. use same address as LR did
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reqCmd := M_XSC
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// Send request
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sendFreshReq := Bool(true)
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// Multi-cycle operation finished
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opInProgress := UInt(0)
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// Move on to a new operation
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currentOp := randOp
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}
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}
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}
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}
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// Sending of requests
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// -------------------
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when (sendFreshReq) {
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// Grab a unique tag for the request
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reqTag := tagMan.io.tagOut
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tagMan.io.take := Bool(true)
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// Fill in unique data
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reqData := Cat(nextData, tid)
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nextData := nextData + UInt(1)
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// Request is good to go!
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reqValid := Bool(true)
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// Increment request count
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reqCount := reqCount + UInt(1)
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}
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.elsewhen (io.mem.req.fire()) {
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// Request has been sent and there is no new request ready
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reqValid := Bool(false)
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}
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// Wire up interface to memory
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io.mem.req.valid := reqValid
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io.mem.req.bits.addr := reqAddr
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io.mem.req.bits.data := reqData
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io.mem.req.bits.typ := UInt(log2Ceil(numBytesInWord))
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io.mem.req.bits.cmd := reqCmd
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io.mem.req.bits.tag := reqTag
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io.mem.invalidate_lr := Bool(false)
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// On cycle when request is actually sent, print it
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when (io.mem.req.fire()) {
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// Short-hand for address
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val addr = io.mem.req.bits.addr
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// Print thread id
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printf("%d:", tid)
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// Print command
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when (reqCmd === M_XRD) {
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printf(" load-req 0x%x", addr)
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}
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when (reqCmd === M_XLR) {
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printf(" load-reserve-req 0x%x", addr)
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}
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when (reqCmd === M_XWR) {
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|
printf(" store-req %d 0x%x", reqData, addr)
|
|
}
|
|
when (reqCmd === M_XSC) {
|
|
printf(" store-cond-req %d 0x%x", reqData, addr)
|
|
}
|
|
when (reqCmd === M_XA_SWAP) {
|
|
printf(" swap-req %d 0x%x", reqData, addr)
|
|
}
|
|
// Print tag
|
|
printf(" #%d", reqTag)
|
|
// Print time
|
|
printf(" @%d\n", cycleCount)
|
|
}
|
|
|
|
// Handling of responses
|
|
// ---------------------
|
|
|
|
// When a response is received
|
|
when (io.mem.resp.valid) {
|
|
// Put tag back in tag set
|
|
tagMan.io.tagIn := io.mem.resp.bits.tag
|
|
tagMan.io.put := Bool(true)
|
|
// Print response
|
|
printf("%d: resp %d #%d @%d\n", tid,
|
|
io.mem.resp.bits.data, io.mem.resp.bits.tag, cycleCount)
|
|
// Increment response count
|
|
respCount := respCount + UInt(1)
|
|
}
|
|
|
|
// Termination condition
|
|
// ---------------------
|
|
|
|
val done = reqCount === UInt(numReqsPerGen) &&
|
|
respCount === UInt(numReqsPerGen)
|
|
|
|
val donePulse = done && !Reg(init = Bool(false), next = done)
|
|
|
|
// Emit that this thread has completed
|
|
when (donePulse) {
|
|
printf(s"FINISHED ${numGens}\n")
|
|
}
|
|
|
|
io.finished := done
|
|
io.timeout := reqTimer.io.timeout.valid
|
|
}
|
|
|
|
|
|
// =======================
|
|
// Trace-generator wrapper
|
|
// =======================
|
|
|
|
class TraceGenTile(val id: Int, val params: TraceGenParams)(implicit p: Parameters) extends GroundTestTile(params) {
|
|
val masterNode: TLOutwardNode = dcacheOpt.map(_.node).getOrElse(TLIdentityNode())
|
|
override lazy val module = new TraceGenTileModuleImp(this)
|
|
}
|
|
|
|
class TraceGenTileModuleImp(outer: TraceGenTile) extends GroundTestTileModuleImp(outer) {
|
|
|
|
val tracegen = Module(new TraceGenerator(outer.params))
|
|
tracegen.io.hartid := constants.hartid
|
|
|
|
outer.dcacheOpt foreach { dcache =>
|
|
val dcacheIF = Module(new SimpleHellaCacheIF())
|
|
dcacheIF.io.requestor <> tracegen.io.mem
|
|
dcache.module.io.cpu <> dcacheIF.io.cache
|
|
}
|
|
|
|
status.finished := tracegen.io.finished
|
|
status.timeout.valid := tracegen.io.timeout
|
|
status.timeout.bits := UInt(0)
|
|
status.error.valid := Bool(false)
|
|
|
|
assert(!tracegen.io.timeout, s"TraceGen tile ${outer.id}: request timed out")
|
|
}
|