56 lines
1.8 KiB
Scala
56 lines
1.8 KiB
Scala
// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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package freechips.rocketchip.groundtest
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.rocket._
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import freechips.rocketchip.tile.CoreModule
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import freechips.rocketchip.util.ParameterizedBundle
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class DummyPTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
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val io = new Bundle {
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val requestors = Vec(n, new TLBPTWIO).flip
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}
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val req_arb = Module(new RRArbiter(new PTWReq, n))
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req_arb.io.in <> io.requestors.map(_.req)
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req_arb.io.out.ready := Bool(true)
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def vpn_to_ppn(vpn: UInt): UInt = vpn(ppnBits - 1, 0)
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class QueueChannel extends ParameterizedBundle()(p) {
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val ppn = UInt(width = ppnBits)
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val chosen = UInt(width = log2Up(n))
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}
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val s1_ppn = vpn_to_ppn(req_arb.io.out.bits.addr)
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val s2_ppn = RegEnable(s1_ppn, req_arb.io.out.valid)
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val s2_chosen = RegEnable(req_arb.io.chosen, req_arb.io.out.valid)
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val s2_valid = Reg(next = req_arb.io.out.valid)
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val s2_resp = Wire(init = 0.U.asTypeOf(new PTWResp))
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s2_resp.pte.ppn := s2_ppn
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s2_resp.pte.reserved_for_software := UInt(0)
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s2_resp.level := UInt(pgLevels-1)
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s2_resp.pte.d := Bool(true)
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s2_resp.pte.a := Bool(true)
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s2_resp.pte.g := Bool(false)
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s2_resp.pte.u := Bool(true)
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s2_resp.pte.r := Bool(true)
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s2_resp.pte.w := Bool(true)
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s2_resp.pte.x := Bool(false)
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s2_resp.pte.v := Bool(true)
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io.requestors.zipWithIndex.foreach { case (requestor, i) =>
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requestor.resp.valid := s2_valid && s2_chosen === UInt(i)
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requestor.resp.bits := s2_resp
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requestor.status := 0.U.asTypeOf(requestor.status)
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requestor.ptbr.mode := requestor.ptbr.pgLevelsToMode(pgLevels).U
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requestor.ptbr.asid := UInt(0)
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requestor.ptbr.ppn := UInt(0)
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}
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}
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