61 lines
1.9 KiB
Plaintext
61 lines
1.9 KiB
Plaintext
# check RISCV environment variable
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ifndef RISCV
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$(error Please set environment variable RISCV. Please take a look at README)
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endif
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MODEL ?= TestHarness
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PROJECT ?= freechips.rocketchip.system
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CFG_PROJECT ?= $(PROJECT)
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CONFIG ?= DefaultConfig
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# TODO: For now must match rocketchip.Generator
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long_name = $(PROJECT).$(CONFIG)
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VLSI_MEM_GEN ?= $(base_dir)/scripts/vlsi_mem_gen
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CXX ?= g++
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CXXFLAGS := -O1
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JVM_MEMORY ?= 2G
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SBT ?= java -Xmx$(JVM_MEMORY) -Xss8M -XX:MaxPermSize=256M -jar $(base_dir)/sbt-launch.jar
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SHELL := /bin/bash
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FIRRTL_JAR ?= $(base_dir)/firrtl/utils/bin/firrtl.jar
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FIRRTL ?= java -Xmx$(JVM_MEMORY) -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver
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# Build firrtl.jar and put it where chisel3 can find it.
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$(FIRRTL_JAR): $(shell find $(base_dir)/firrtl/src/main/scala -iname "*.scala")
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$(MAKE) -C $(base_dir)/firrtl SBT="$(SBT)" root_dir=$(base_dir)/firrtl build-scala
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touch $(FIRRTL_JAR)
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mkdir -p $(base_dir)/lib
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cp -p $(FIRRTL_JAR) $(base_dir)/lib
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# When chisel3 pr 448 is merged, the following extraneous copy may be removed.
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mkdir -p $(base_dir)/chisel3/lib
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cp -p $(FIRRTL_JAR) $(base_dir)/chisel3/lib
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src_path := src/main/scala
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default_submodules := . hardfloat chisel3
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chisel_srcs := $(foreach submodule,$(default_submodules) $(ROCKETCHIP_ADDONS),$(shell find $(base_dir)/$(submodule)/$(src_path) -name "*.scala"))
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disasm := 2>
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which_disasm := $(shell which spike-dasm 2> /dev/null)
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ifneq ($(which_disasm),)
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disasm := 3>&1 1>&2 2>&3 | $(which_disasm) $(DISASM_EXTENSION) >
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endif
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timeout_cycles = 100000000
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bootrom_img = $(base_dir)/bootrom/bootrom.img
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#--------------------------------------------------------------------
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# Build Tests
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#--------------------------------------------------------------------
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%.hex:
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$(MAKE) -C $(dir $@) $(notdir $@)
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%.riscv.hex: %.riscv
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$(MAKE) -C $(dir $@) $(notdir $@)
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clean-run-output:
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rm -f $(output_dir)/{*.out,*.run,*.vpd}
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