Add small rocket config with fpu and mmu

This is required for booting linux. The caches are still as small as
in the small core config, so performance will not be great.

scripts/vlsi_rom_gen

@@ -23,9 +23,6 @@ module {name}(
   reg [{output_width_minus_1}:0] rom [0:{depth_minus_1}];
 
 
-  // 1024 is the maximum length of $readmemh filename supported by Cadence Incisive
-  reg [1024 * 8 - 1:0] path;
-
   integer i;
   initial begin
 `ifdef RANDOMIZE
@@ -35,10 +32,7 @@ module {name}(
     end
   `endif
 `endif
-    if (!$value$plusargs("maskromhex=%s", path)) begin
+    $readmemh("{rom_hex_file}", rom);
-      path = "{rom_hex_file}";
-    end
-    $readmemh(path, rom);
   end
 
 

src/main/scala/subsystem/Configs.scala

@@ -50,6 +50,28 @@ class WithNBigCores(n: Int) extends Config((site, here, up) => {
   }
 })
 
+class WithNSmallLinuxCores(n: Int) extends Config((site, here, up) => {
+  case RocketTilesKey => {
+    val small = RocketTileParams(
+      core = RocketCoreParams(),
+      btb = None,
+      dcache = Some(DCacheParams(
+        rowBits = site(SystemBusKey).beatBits,
+        nSets = 64,
+        nWays = 1,
+        nTLBEntries = 4,
+        nMSHRs = 0,
+        blockBytes = site(CacheBlockBytes))),
+      icache = Some(ICacheParams(
+        rowBits = site(SystemBusKey).beatBits,
+        nSets = 64,
+        nWays = 1,
+        nTLBEntries = 4,
+        blockBytes = site(CacheBlockBytes))))
+    List.tabulate(n)(i => small.copy(hartId = i))
+  }
+})
+
 class WithNSmallCores(n: Int) extends Config((site, here, up) => {
   case RocketTilesKey => {
     val small = RocketTileParams(