rocket-chip

riscv/rocket-chip

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Author	SHA1	Message	Date
Andrew Waterman	8225676a86	For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaN See https://github.com/riscv/riscv-isa-sim/issues/76	2017-02-02 11:55:08 -08:00
Wesley W. Terpstra	e5af59db68	rocketchip: work-around ucb-bar/chisel3#472	2017-01-31 14:20:02 -08:00
Henry Cook	74b6a8d02b	Refactor Tile to use cake pattern (#502 ) * [rocket] Refactor Tile into cake pattern with traits * [rocket] cacheDataBits &etc in HasCoreParameters * [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters * [rocket] frontend and icache now diplomatic * [rocket] file name capitalization * [rocket] re-add hook for inserting externally-defined Cores * [rocket] add FPUCoreIO * [groundtest] move TL1 Config instances to where they are used * [unittest] remove legacy unit tests * [groundtest] remove legacy device tests	2017-01-16 18:24:08 -08:00

Author

SHA1

Message

Date

Andrew Waterman

8225676a86

For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaN

See https://github.com/riscv/riscv-isa-sim/issues/76

2017-02-02 11:55:08 -08:00

Wesley W. Terpstra

e5af59db68

rocketchip: work-around ucb-bar/chisel3#472

2017-01-31 14:20:02 -08:00

Henry Cook

74b6a8d02b

Refactor Tile to use cake pattern (#502 )

* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests

2017-01-16 18:24:08 -08:00

3 Commits