Yunsup Lee
|
70b0f9fd4d
|
error out for PCWM-L, port width mismatch
|
2014-09-25 06:50:50 -07:00 |
|
Yunsup Lee
|
275b72368b
|
add CONFIG to the name of simulator executable
|
2014-09-11 22:11:58 -07:00 |
|
Yunsup Lee
|
5f8bd18fac
|
Makefiles should be perfect
|
2014-09-11 02:53:46 -07:00 |
|
Yunsup Lee
|
02c08a156f
|
generate consts.vh from chisel source
|
2014-09-10 17:14:55 -07:00 |
|
Yunsup Lee
|
ddfd3ce968
|
further generalize fpga/vlsi builds
|
2014-09-08 00:21:57 -07:00 |
|
Yunsup Lee
|
763c57931b
|
fix problem introduced with verilog generation in vsim/fsim
|
2014-09-04 09:49:57 -07:00 |
|
Yunsup Lee
|
c03c09ec31
|
update for rocket-chip release
|
2014-08-31 20:26:55 -07:00 |
|