riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
5,187 Commits 1 Branch 0 Tags
ef28ce8d2f1809d9da2d2b094e3ac776f4b8c51e
Commit Graph
3 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
Henry Styles 5498468743 FPU : simplify pipeline register generation in FMA 2017-10-05 15:18:19 -07:00
Henry Styles 7a46715cbc FPU : to assist retiming move upto first 2 register stages of into FMA 2017-10-05 15:18:04 -07:00
Henry StylesandWesley W. Terpstra f7330028cc Add optional frontbus for peripherals mastering into SBus. Switch FF and Buffer order on non-tile masters into SBus. Buffer non-L2 side of splitter 2017-08-30 14:22:49 -07:00