10 Commits

Author	SHA1	Message	Date
Wesley W. Terpstra	e831acba9c	adapters: support bulk connections	2017-09-07 16:03:35 -07:00
Wesley W. Terpstra	2e4f1611ed	tilelink: Error device supports Acquire ... We need this if we want to divert traffic to it from a TL-C slave.	2017-07-27 18:32:58 -07:00
Henry Cook	01ca3efc2b	Combine Coreplex and System Module Hierarchies (#875) ... * coreplex collapse: peripherals now in coreplex * coreplex: better factoring of TLBusWrapper attachement points * diplomacy: allow monitorless :*= and :=* * rocket: don't connect monitors to tile tim slave ports * rename chip package to system * coreplex: only sbus has a splitter * TLFragmenter: Continuing my spot battles on requires without explanatory strings * pbus: toFixedWidthSingleBeatSlave * tilelink: more verbose requires * use the new system package for regression * sbus: add more explicit FIFO attachment points * delete leftover top-level utils * cleanup ResetVector and RTC	2017-07-23 08:31:04 -07:00
Wesley W. Terpstra	9310a33e77	apb: SRAM can emulate incompletely populated memory	2017-07-07 21:40:40 -07:00
Wesley W. Terpstra	28fbf1af8e	ahb: SRAM can emulate incompletely populated memory	2017-07-07 21:40:39 -07:00
Wesley W. Terpstra	df44b23956	axi4: SRAM can emulate incompletely populated memory	2017-07-07 21:40:39 -07:00
Wesley W. Terpstra	f1fb3be603	ahb: SRAM reports errors on illegal access	2017-07-07 21:15:36 -07:00
Wesley W. Terpstra	19851a7c9e	apb: SRAM reports errors on illegal access	2017-07-07 21:15:33 -07:00
Wesley W. Terpstra	025f7d890b	axi4: SRAM now reports errors on illegal address (#852)	2017-07-07 19:27:32 -07:00
Henry Cook	4c595d175c	Refactor package hierarchy and remove legacy bus protocol implementations (#845) ... * Refactors package hierarchy. Additionally: - Removes legacy ground tests and configs - Removes legacy bus protocol implementations - Removes NTiles - Adds devices package - Adds more functions to util package	2017-07-07 10:48:16 -07:00