134 Commits

Author	SHA1	Message	Date
Richard Xia	5a951799aa	Add atomics support to DTS JSON file.	2017-10-18 15:17:53 -07:00
Henry Cook	1852ccd8f3	Merge pull request #1053 from freechipsproject/resource-cacheable ... tilelink: cacheable resource permission	2017-10-12 17:49:49 -07:00
Wesley W. Terpstra	8b58327fa4	axi4: conversion from TL does not need beatBytes (#1051) ... We used to pack the addr_lo into user bits. We don't do that anymore. There is thus no need to waste those bits, nor to pass that arg.	2017-10-12 16:41:54 -07:00
Henry Cook	ad243ef9f5	tilelink: cacheable resource permission now reports whether a address space could possibly be cached, even if no visible adapters make it so	2017-10-12 13:49:40 -07:00
Henry Cook	66e4bfc2d9	rocket: TIMs should never be cached	2017-10-11 18:22:52 -07:00
Henry Cook	329a5c35d4	tilelink: unsafe cache cork discards outer d.sink	2017-10-11 00:30:51 -07:00
Henry Cook	1867a5b226	rocket: only cache when AcquireT is possible	2017-10-10 18:06:58 -07:00
Henry Cook	37406706b4	coreplex: move CacheCork in front of SBus ... Continue to not allow caches to cache ROMs. Update TinyConfig and WithStatelessBridge.	2017-10-10 16:24:32 -07:00
Wesley W. Terpstra	bd045a3b95	tilelink: split Acquire into Acquire{Block,Perm} (#1030) ... We had planned for a while to add an 'Overwrite' message which obtains permissions without requiring retrieval of data. This is useful whenever a master knows it will completely replace the contents of a cache block. Instead of calling it Overwrite, we decided to split the Acquire type. If you AcquirePerm, you MUST Release and ProbeAck with Data.	2017-10-05 12:49:49 -07:00
Wesley W. Terpstra	a2dc13669a	Error grants (#1025) ... * CacheCork: an error Grant still says 'toT' even though it is transient Grants with errors must be handled by a client as though no actual permissions were obtained, so that two clients do not both end up believing that they own a block which is only temporarily offline. However, the Grant MESSAGE should still match the request; ie. if you did Acquire.NtoT, the response must be Grant.toT, even though the 'error' bit signals that the Grant actually grants no permissions. This keeps the implementation of request-response tracking in interstitial adapters and FSMs simple, consistent with the way multibeat errors must include all their beats. * Error: handle permissions properly	2017-10-02 14:49:25 -07:00
Henry Cook	547bdc2b5b	diplomacy: standardize sram device resource naming (#1022)	2017-09-29 14:52:26 -07:00
Wesley W. Terpstra	ce01ab2700	RegisterRouter: correctly create interrupts vector	2017-09-27 12:27:16 -07:00
Wesley W. Terpstra	31a934bec0	coreplex: buses are now LazyModules with LazyScope	2017-09-26 14:58:56 -07:00
Wesley W. Terpstra	a27e853101	diplomacy: move rendering properties to edges ... FlipRendering { implicit p => ... } now changes the render direction of edges. diplomatic NodeImps can specify a default render flip using the new 'render' method.	2017-09-26 13:24:36 -07:00
Wesley W. Terpstra	76c2aa1661	diplomacy: introduce the typing-saving SimpleNodeImp	2017-09-26 12:28:59 -07:00
Wesley W. Terpstra	60614055e3	diplomacy: eliminate some wasted IdentityNodes using cross-module refs	2017-09-25 12:06:27 -07:00
Wesley W. Terpstra	bc225a4e82	diplomacy: place Monitors inside LazyModules sinks ... We used to place Monitors at the point of the ':='. This was problematic because the clock domain might be wrong. Thus, we needed to shove Monitors a lot. Furthermore, now that we have cross-module ':=', you might not even have access to the wires at the point where ':=' is invoked.	2017-09-22 23:36:17 -07:00
Wesley W. Terpstra	cfb7f13408	diplomacy: capture SourceInfo at point of := in Edge parameters	2017-09-22 22:25:56 -07:00
Wesley W. Terpstra	b9a2e4c243	diplomacy: API beautification	2017-09-22 15:01:42 -07:00
Wesley W. Terpstra	9217baf9d4	diplomacy: change API to auto-create node bundles => cross-module refs	2017-09-22 15:01:39 -07:00
Wesley W. Terpstra	53f6999ea8	Splitter: reuse TLCustom node instead of special diplomacy case	2017-09-22 14:58:39 -07:00
Wesley W. Terpstra	1fedabcb55	tilelink: invoke LazyModule() at point of monitor binding	2017-09-22 14:38:47 -07:00
Wesley W. Terpstra	d89ee9d9d4	nodes: grab a name on construction	2017-09-22 14:38:47 -07:00
Jacob Chang	b4fc5104d4	Add cover property API that can be refined through Config PropertyLibrary (#998)	2017-09-19 19:26:54 -07:00
Henry Cook	e50d14415e	tilelink: more verbose requires	2017-09-13 11:25:42 -07:00
Henry Cook	b86f4b9bb7	config: use Field defaults over Config defaults ... Also rename some keys that had the same class name as their value's class name.	2017-09-13 11:25:42 -07:00
Wesley W. Terpstra	6879f5bfb1	tilelink: Xbar now allows for fanout control	2017-09-07 16:03:35 -07:00
Wesley W. Terpstra	e831acba9c	adapters: support bulk connections	2017-09-07 16:03:35 -07:00
Wesley W. Terpstra	06a244f9f9	diplomacy: rename {Left,Right}Star to refer to {Source,Sink}Cardinality	2017-09-07 16:03:35 -07:00
Wesley W. Terpstra	a450357744	tilelink: Monitor construction method is unconditional ... Whether or not a Monitor should be placed is decided by diplomacy.	2017-09-07 16:03:35 -07:00
Wesley W. Terpstra	42f1ae27fc	Xbar: use the IdentityModule to encourage wider fanout	2017-09-07 16:03:35 -07:00
Wesley W. Terpstra	4911a7d44f	tilelink Bus: toAsyncSlaves now supports BufferChains	2017-09-07 16:03:35 -07:00
Wesley W. Terpstra	040f7e1d49	tilelink: add Bus.toSyncSlaves for easy BufferChain attachment	2017-09-07 16:03:35 -07:00
Wesley W. Terpstra	d5c6494f59	tilelink: Bus.toRationalSlaves can have a BufferChain	2017-09-07 16:03:35 -07:00
Wesley W. Terpstra	80965e8230	tilelink Buffer: use new :=? adapter API	2017-09-07 16:03:35 -07:00
Megan Wachs	dcafb5fea3	Merge remote-tracking branch 'origin/master' into async_reg	2017-09-06 11:07:19 -07:00
Megan Wachs	667d966410	TLBuffer: Create a wrapper module for TLBufferChain, to allow for more stable naming	2017-09-05 15:03:38 -07:00
Megan Wachs	c353f68dc0	buses: name dummy buffers too	2017-09-05 15:03:38 -07:00
Henry Cook	3bde9506c6	coreplex: allow buffer chains on certain bus ports	2017-09-05 15:03:36 -07:00
Megan Wachs	c99afe4c66	buses: Name all the things.	2017-08-30 17:31:42 -07:00
Henry Cook	32cb358c81	coreplex: include optional tile name for downstream name stabilization	2017-08-30 15:48:55 -07:00
Megan Wachs	a62ce0afe6	TLBuffer: Add a nodedebugstring for quick browsing of the properties of the buffer.	2017-08-29 10:36:46 -07:00
Megan Wachs	130b24355f	syncregs: Use synchronizer primitives for IntXing	2017-08-24 17:39:07 -07:00
Wesley W. Terpstra	f191bb994c	PatternPusher: can now expect a certain output (#952)	2017-08-11 18:10:27 -07:00
Wesley W. Terpstra	baf769f924	tilelink: add PatternPusher, a device to inject a fixed traffic pattern (#950)	2017-08-11 15:07:10 -07:00
Henry Cook	c8f8806df0	Merge pull request #932 from freechipsproject/tl-bus-delayer ... tilelink: allow insertion of TLDelayer on TLBus outward node	2017-08-07 19:01:39 -07:00
Henry Cook	c4092dd0cc	tilelink: improve entropy of bus delayer	2017-08-07 17:36:07 -07:00
Henry Cook	2910d6fa2a	tilelink: make bus xbar protected so it can be suggestNamed	2017-08-07 17:30:24 -07:00
Henry Cook	c457c9cb9f	tilelink: allow insertion of TLDelayer on TLBus outward node	2017-08-07 16:43:06 -07:00
Wesley W. Terpstra	f8b45564d1	tilelink: RAMModel must support source reuse ... If a multibeat response comes back, the source might be reused. If response reordering has made the multibeat response invalid, we need to remember this even if the valid bit is cleared on reuse.	2017-08-07 16:01:15 -07:00