Wesley W. Terpstra
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5edc4546e3
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rocket: add dtim and itim refs to cpus
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2017-06-28 23:10:58 -07:00 |
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Wesley W. Terpstra
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7d6f8d48f2
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Revert "rocket: link dtim to its cpu"
This reverts commit e6c2d446cc.
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2017-06-28 23:10:57 -07:00 |
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Wesley W. Terpstra
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fbcd6f0eb2
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Revert "rocket: link itim to its cpu"
This reverts commit 48390ed604.
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2017-06-28 23:10:57 -07:00 |
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Wesley W. Terpstra
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48390ed604
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rocket: link itim to its cpu
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2017-06-28 15:06:19 -07:00 |
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Wesley W. Terpstra
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e6c2d446cc
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rocket: link dtim to its cpu
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2017-06-28 15:06:19 -07:00 |
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Wesley W. Terpstra
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3f6d5110cd
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rocket: dtim is not a dcache
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2017-06-28 15:06:19 -07:00 |
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Colin Schmidt
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aced18b3bb
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Move RoCC interface to Diplomacy and TL2 (#807)
* Move RoCC interface to Diplomacy and TL2
* guard rocc arbiter to prevent zero-width wires
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2017-06-22 12:07:09 -07:00 |
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Henry Cook
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a19fc2549e
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tile: add tileBus xbar
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2017-05-16 16:12:01 -07:00 |
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