Logo
Explore Help
Sign In
riscv/rocket-chip
Watch 1
Star 0
Fork 0
Code Releases Activity
5,516 Commits 1 Branch 0 Tags
b95f68447f47ae2a1ec0038c5a706ec6f72d0561
Commit Graph
3 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
Henry Styles 5498468743 FPU : simplify pipeline register generation in FMA 2017-10-05 15:18:19 -07:00
Henry Styles 7a46715cbc FPU : to assist retiming move upto first 2 register stages of into FMA 2017-10-05 15:18:04 -07:00
Henry Styles f7330028cc Add optional frontbus for peripherals mastering into SBus. Switch FF and Buffer order on non-tile masters into SBus. Buffer non-L2 side of splitter 2017-08-30 14:22:49 -07:00
Powered by Gitea Version: 1.27.3 Page: 59ms Template: 2ms
Dark
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API