Yunsup Lee
56d81b0034
fix configstring printout with no memory
2016-09-06 10:40:11 -07:00
Andrew Waterman
63679bb019
Add support for L1 data scratchpads instead of caches
...
They fit in the same part of the address space as DRAM would be, and
are coherent (because they are not cacheable).
They are currently limited to single cores without DRAM. We intend
to lift both restrictions, probably when we add support for
heterogeneous tiles.
2016-09-02 16:22:07 -07:00
Megan Wachs
af364bc7bc
Rename RTC to RTCTick to clarify that it needs to be a Boolean signal, not a Clock type signal
2016-09-02 15:14:39 -07:00
Megan Wachs
8163a6b597
Make it easier to override the 'placeholder' Real-Time-Clock, to allow more real-world applications
2016-09-02 11:11:40 -07:00
SeungRyeol Lee
b1ce3b8c98
Add address map entries for exported mmio port.
2016-08-31 06:58:38 +09:00
Megan Wachs
53ee54dbd1
Incorporate feedback to make the NExtPerhipheryInterrupts come from DeviceBlock itself
2016-08-26 10:40:39 -07:00
Megan Wachs
428eed79a1
Allow some External Interrupts to come from Periphery
2016-08-25 14:16:33 -07:00
Megan Wachs
9974626d6a
Merge remote-tracking branch 'origin/master' into HEAD
...
Conflicts:
src/main/scala/rocketchip/TestHarness.scala
2016-08-23 07:34:01 -07:00
Howard Mao
61aa716f44
fix bus axi connections in periphery
2016-08-22 11:57:15 -07:00
Howard Mao
f9ea14b4c2
extra devices should get elaborated in a single build function
2016-08-22 11:57:15 -07:00
Megan Wachs
dd4a50c452
Add JTAG DTM and test support in simulation
...
Initial cut
checkpoint which compiles and runs but there is some off-by-1 in the protocol
Debugging the clock crossing logic
checkpoint which works
Clean up the AsyncMailbox black box
2016-08-19 16:08:17 -07:00
Howard Mao
f4e0e0966c
move rocketchip package sources into its own subdirectory
2016-08-19 13:45:23 -07:00
