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riscv/rocket-chip
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17 Commits 1 Branch 0 Tags
98a5d682a59c3a183145ce85628f58e11e8febcf
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12 Commits
Author SHA1 Message Date
Andrew Waterman 98a5d682a5 coherence mostly works now 2012-04-10 02:22:45 -07:00
Henry Cook 1920c97066 Refactored coherence as member rather than trait. MI and MEI protocols. 2012-04-10 00:09:58 -07:00
Henry Cook 5acf1d9820 defined abstract coherence traits in base trait, added Incoherent trait, cleaned up incoherent policy 2012-04-09 23:29:32 -07:00
Henry Cook a68f5e016d changed coherence type width names to represent max sizes for all protocols 2012-04-09 23:29:32 -07:00
Henry Cook f7307ee411 changed coherence message type names 2012-04-09 23:29:31 -07:00
Henry Cook d301336c33 Refactored coherence better from uncore hub, better coherence function names 2012-04-09 23:29:31 -07:00
Andrew Waterman 257747a3a1 no dessert tonight :( 2012-03-26 23:50:09 -07:00
Andrew Waterman 25fe46dc18 remove bug from dessert 2012-03-26 14:18:57 -07:00
Andrew Waterman 4e6302fedc add dessert 2012-03-25 23:03:20 -07:00
Andrew Waterman 5a00143035 loop host.in to host.out during reset 2012-03-25 21:45:10 -07:00
Andrew Waterman a7ebea13fc add mem serdes unit 2012-03-25 17:03:58 -07:00
Andrew Waterman 3129040bda use divided clk for htif. UDPATE YOUR FESVR
by default, we now load programs via a backdoor, because otherwise
it takes too long to simulate.
2012-03-15 18:36:51 -07:00
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