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riscv/rocket-chip
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Code Releases Activity
2,965 Commits 1 Branch 0 Tags
8e0392f24b6bcb644d2922123e0828985f12b5a6
Commit Graph
112 Commits
Author SHA1 Message Date
Howard Mao 4c3c3c630e add assertions to make sure NASTI -> MemIO converter takes in requests of the right size and len 2015-09-10 17:55:10 -07:00
Howard Mao 6387d31c62 add comments and small fixes for NASTI and SMI 2015-09-10 17:33:48 -07:00
Howard Mao 8a8d52da4f add convenient constructors for NASTI channels 2015-09-10 17:33:31 -07:00
Howard Mao ede1ada053 Add converters and utilities for simpler peripheral interface (SMI) 2015-09-01 14:00:45 -07:00
Howard Mao 75ec7529af implement NASTI Interconnect generating from configuration address map 2015-09-01 14:00:45 -07:00
Howard Mao b046c57284 make NASTI -> MemIO converter compliant to AXI4 spec 2015-09-01 11:17:38 -07:00
Andrew Waterman f7d9628de2 Avoid needless use of Vec 2015-08-27 09:40:52 -07:00
Andrew Waterman 3a1dad7994 Use Vec.apply, not Vec.fill, for type nodes 2015-08-27 09:40:24 -07:00
Andrew Waterman 2ff2b43c2c Chisel3 compatibility: use >>Int instead of >>UInt
The latter doesn't contract widths anymore.
2015-08-04 13:13:44 -07:00
Andrew Waterman d85c46bc60 Chisel3 bulk connect non-commutativity 2015-08-03 19:47:16 -07:00
Andrew Waterman eb57433f43 Bits -> UInt 2015-07-30 23:57:53 -07:00
Henry Cook c27945c094 source and build files. source code pulled from uncore and zscale repos 2015-07-29 18:02:58 -07:00
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