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Commit Graph

15 Commits

Author SHA1 Message Date
Howard Mao
bbf14ddc01 use definitions in consts header whenever possible 2015-11-05 10:48:32 -08:00
Howard Mao
ba5a6af05c correctly stripe data across memory channels in simulation 2015-11-05 10:48:32 -08:00
Yunsup Lee
0d245741bc add multichannel NASTI support in Verilog testbench 2015-11-05 10:48:32 -08:00
Howard Mao
9dabcab9c2 Get rid of MemIO in Top and replace with AXI throughout 2015-11-05 10:48:32 -08:00
Howard Mao
c517d9f6e3 fix htif emulator constructor in vcs_main 2015-09-25 17:21:09 -07:00
Yunsup Lee
1cfd9f5a0e add LICENSE 2014-09-12 10:15:04 -07:00
Yunsup Lee
d2c32b048a fix bug in htif_fini, need to use vc_handle! 2014-03-18 01:35:08 -07:00
Andrew Waterman
0d124d283a Write our own vcs main() routine 2014-03-17 17:02:28 -07:00
Andrew Waterman
c55eee7244 Pass target machine exit code back to host OS 2013-10-29 13:24:09 -07:00
Andrew Waterman
ae0716fb6d Use chisel printf for logging 2013-06-13 10:53:23 -07:00
Andrew Waterman
cfa86dba4f add FPGA test bench
The memory models now support back pressure on the response.
2013-05-02 04:59:32 -07:00
Andrew Waterman
d2e1828714 gracefully kill htif thread, fixing tty stuff 2013-05-02 04:59:32 -07:00
Andrew Waterman
4077b22929 include fesvr as a library; improve harnesses 2013-01-24 23:57:23 -08:00
Andrew Waterman
d911e635d6 simplify c++ memory models; support +dramsim flag
works for both vlsi and emulator
2012-12-04 07:04:26 -08:00
Huy Vo
93a0182b96 everything to get emulator working 2012-10-01 19:30:11 -07:00