riscv
/
rocket-chip
1
0
Fork 0
Code Releases Activity
5,576 Commits 1 Branch 0 Tags 13 MiB
Commit Graph

22 Commits

Author SHA1 Message Date
Megan Wachs 451334ac73 Add 1-deep synchronizer register for output of AsyncQueue 2017-08-28 17:18:54 -07:00
Megan Wachs 8b462d1595 syncregs: Use common primitives for AsyncQueue grey code synchronizers 2017-08-24 17:34:07 -07:00
Henry Cook 4c595d175c Refactor package hierarchy and remove legacy bus protocol implementations (#845) 
* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package
 2017-07-07 10:48:16 -07:00
Ben Keller 0aa8f7d61d Add narrowData option to AsyncQueue. 
This option reduces the number of wires that cross the clock boundary.
This can be a useful feature if the clock boundary coincides with
a voltage boundary, in which case the number of level shifters is reduced.
However, this introduces a path that crosses from sink->source->sink domain,
so the option is disabled by default.
 2017-04-21 16:31:17 -07:00
Wesley W. Terpstra b7963eca4e copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
Jacob Chang fc5eb7cc64 Fixed AsyncFifo with reset messaging 2016-10-25 16:45:08 -07:00
Wesley W. Terpstra ac0bb841da AsyncQueue: cope with far reset propagation delay 2016-10-14 18:05:35 -07:00
Wesley W. Terpstra 1b09f1360d AsyncQueue: adjust register names to match vals 2016-10-10 13:13:32 -07:00
Wesley W. Terpstra e7f8a7e9ea AsyncQueue: make it clear that the SyncChain is not Gray specific 2016-10-10 13:13:32 -07:00
Wesley W. Terpstra 52b8121e68 Apply "async_queue: Give names to all the registers which show up in the queue (#390)" 
Adjusted to include names for the new registers.
Changes to RegisterCrossing were discarded.
 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra ffb734ac0e AsyncQueue: disambiguiate the reset_n signal names 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra 5ee53c61d6 util: clarify an AsyncQueue corner-case 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra 609fd97a71 util: AsyncQueue detect power-down/reset of non-empty queue 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra 75bb94017b util: resynchronize AsyncQueue counters when far side resets 
If the other clock domain is much faster than ours, it's reset
might be shorter than a single cycle in our domain. In that case,
we need to catch the reset and extend it.
 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra 5e2609bdd2 AsyncQueueSource: don't feed reset into normal logic! 
There is no need to block writes to mem during reset.
The Queue must be empty anyway.
 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra 2f6985efd3 crossings: use flip not flip() 
This seems to be the more common API
 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra cb7b16f1a9 util: exchange resets between AsyncQueue source and sink 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra 8c7d469a95 Revert "async_queue: Give names to all the registers which show up in the queue (#390)" 
This reverts commit a84a961a39.

The changes to RegisterCrossing.scala were unneeded after application of this branch.
The name changes made to the AsyncQueue.scala are reapplied at the end of this branch.
 2016-10-10 13:13:31 -07:00
mwachs5 a84a961a39 async_queue: Give names to all the registers which show up in the queue (#390) 
This is to aid debugging but even more so for backend constraint writers, who generally
need predictable names for registers to set false paths, etc.
 2016-10-08 17:50:50 -07:00
mwachs5 e952f8f222 asyncqueue: Fix typo in the Async Queue (#381) 
* asyncqueue: Fix typo in the Async Queue that would cause the sync depth to be one less than expected.

* asyncqueue: Typo in the typo fix
 2016-10-04 21:02:06 -07:00
Wesley W. Terpstra 20f42a8762 tilelink2: reuse the halves of the AsyncQueue 2016-09-29 17:35:08 -07:00
Howard Mao 9910c69c67 Move a bunch more things into util package 
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were

 * The AsyncQueue and AsyncDecoupledCrossing from junctions.
 * All of the code in rocket's util.scala
 * The BlackBox asynchronous reset registers from uncore.tilelink2
 * The implicit definitions from uncore.util
 2016-09-29 14:23:42 -07:00