3 Commits

Author	SHA1	Message	Date
Colin Schmidt	a10d058e1a	fix warnings in verilog source (#274)	2016-09-12 18:25:35 -07:00
Yunsup Lee	4a7972be31	connect testharness components via member functions (#236) ... to prevent code duplication for new testbenches	2016-09-01 18:38:39 -07:00
Megan Wachs	dd4a50c452	Add JTAG DTM and test support in simulation ... Initial cut checkpoint which compiles and runs but there is some off-by-1 in the protocol Debugging the clock crossing logic checkpoint which works Clean up the AsyncMailbox black box	2016-08-19 16:08:17 -07:00