riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
5,228 Commits 1 Branch 0 Tags 13 MiB
7453186b59
Commit Graph

2050 Commits

Author SHA1 Message Date
Wesley W. Terpstra
7453186b59 diplomacy: add reflection for parent modules to nodes 2017-10-25 16:56:50 -07:00
Christopher Celio
c4978712c9 csr: allow for superscalar decode (#1069) 
* CSR provides a decode port to check for an illegal instruction.
   * This commit now allows for multiple instructions in decode to get this
      illegal instruction information.
   * This commit leverages the existing decodeWidth parameter. This will
      potentially over-provision the number of decode ports needed for
      RVC-enabled cores.

Closes #1068
 2017-10-25 13:58:26 -07:00
Wesley W. Terpstra
82b1aa8116 coreplex: print the A first to look nicer 2017-10-18 16:52:35 -07:00
Wesley W. Terpstra
a1ac23d7ec coreplex: continue to print the device name in the address map 2017-10-18 16:44:53 -07:00
Richard Xia
5a951799aa Add atomics support to DTS JSON file. 2017-10-18 15:17:53 -07:00
Megan Wachs
e9e05b5f3b Add a check that MaxHartIdBits is enough for all hartids (#1054) 
* Add a check that MaxHartIdBits is enough for all hartids

* Correct off-by-one error in hartid check
 2017-10-13 15:20:35 -07:00
Henry Cook
1852ccd8f3 Merge pull request #1053 from freechipsproject/resource-cacheable 
tilelink: cacheable resource permission
 2017-10-12 17:49:49 -07:00
Wesley W. Terpstra
8b58327fa4 axi4: conversion from TL does not need beatBytes (#1051) 
We used to pack the addr_lo into user bits. We don't do that anymore.
There is thus no need to waste those bits, nor to pass that arg.
 2017-10-12 16:41:54 -07:00
Andrew Waterman
21b5367259 Expand C.UNIMP correctly (#1052) 
It was expanding to AMOADD.W, which is clearly not an illegal instruction.
 2017-10-12 14:00:14 -07:00
Henry Cook
ad243ef9f5 tilelink: cacheable resource permission now reports whether a address space could possibly be cached, even if no visible adapters make it so 2017-10-12 13:49:40 -07:00
Henry Cook
ad543e5bb6 Merge pull request #1050 from freechipsproject/uncacheable-tims 
rocket: TIMs should never be cached
 2017-10-12 13:04:00 -07:00
Wesley W. Terpstra
f82e441426 axi4: implement a diplomatic AXI4 clock crossing (#1049) 2017-10-12 00:05:45 -07:00
Henry Cook
66e4bfc2d9 rocket: TIMs should never be cached 2017-10-11 18:22:52 -07:00
Henry Cook
b64609bfe8 Merge pull request #1039 from freechipsproject/tile-crossing-params 
Improvements wrt connecting RocketTiles to SystemBus
 2017-10-11 17:12:03 -07:00
Megan Wachs
7b4c48d005 Correctly hook up the Local Interrupts into the Coreplex. Name some IntXBars 2017-10-11 15:10:50 -07:00
Henry Cook
60934ac622 coreplex: TilePortParams use BasicBusBlockers 2017-10-11 13:36:46 -07:00
Henry Cook
2dbe882e58 tilelink: add BasicBusBlocker device 2017-10-11 13:36:42 -07:00
Henry Cook
9f8e3d8879 tilelink: BusBypass can be sent to DeadlockDevice 2017-10-11 12:45:36 -07:00
Henry Cook
ec056535dc tilelink: add DeadlockDevice 2017-10-11 12:44:23 -07:00
Wesley W. Terpstra
b566ffedea system: fix DefaultFPGAConfig (#1047) 
It was missing cores. Fixes #736.
 2017-10-11 10:48:41 -07:00
Henry Cook
329a5c35d4 tilelink: unsafe cache cork discards outer d.sink 2017-10-11 00:30:51 -07:00
Henry Cook
1240cb275c coreplex: TilePortParams formatting 2017-10-11 00:29:11 -07:00
Wesley W. Terpstra
5d62c321f4 generator: create annotation file 2017-10-10 23:23:06 -07:00
Henry Cook
75345b6048 rocket: don't remove ports on top module 2017-10-10 21:28:59 -07:00
Wesley W. Terpstra
b3bdf5eca6 RegField: default argument for .bytes 2017-10-10 19:49:35 -07:00
Wesley W. Terpstra
e094b94ce5 clint: use RegField.toBytes to save some work 2017-10-10 19:49:35 -07:00
Wesley W. Terpstra
10472b4296 diplomacy: auto connect bundles in a stable order (#1045) 2017-10-10 19:41:46 -07:00
Henry Cook
1867a5b226 rocket: only cache when AcquireT is possible 2017-10-10 18:06:58 -07:00
Andrew Waterman
b2bc46471b Conditionalize some covers that are sometimes impossible (#1043) 2017-10-10 17:14:33 -07:00
Henry Cook
37406706b4 coreplex: move CacheCork in front of SBus 
Continue to not allow caches to cache ROMs.
Update TinyConfig and WithStatelessBridge.
 2017-10-10 16:24:32 -07:00
Henry Cook
8f5f80f958 coreplex: TileSlavePortParams inject adapters into PBus 2017-10-10 15:25:08 -07:00
Henry Cook
660355004e coreplex: TileMasterPortParams inject adapters into SBus 2017-10-10 15:02:50 -07:00
Andrew Waterman
50429daef4 Merge pull request #1036 from freechipsproject/l1-cover 
Add some covers for L1 memory system
 2017-10-10 12:28:48 -07:00
Henry Cook
9026646459 coreplex: first cut at using RocketCrossingParams 2017-10-10 12:02:04 -07:00
Wesley W. Terpstra
d6766a8c68 RocketTile: make sure 'hartid' is available for traits (#1037) 2017-10-09 21:03:18 -07:00
Andrew Waterman
1474ab438d Remove extraneous signal 2017-10-09 18:33:50 -07:00
Andrew Waterman
f3825270c1 Add some covers for L1 memory system 2017-10-09 18:33:36 -07:00
Andrew Waterman
2c4009a138 Fix paddrBits < xLen && paddrBits == vaddrBits case 
Require and/or force vaddrBits to be bigger than paddrBits so there's
room to zero-extend a physical address by 1 bit, so that when the virtual
address is sign-extended, the sign is zero.
 2017-10-09 16:48:04 -07:00
Megan Wachs
0e6aa7ae9d Merge pull request #1024 from freechipsproject/jtag_coverage 
Add Coverage points for JTAG TAP
 2017-10-09 12:29:18 -07:00
Megan Wachs
0916cf1bdd JTAG Coverage: Correct jtag_reset case 2017-10-09 09:54:15 -07:00
Megan Wachs
9efe1c448e Merge remote-tracking branch 'origin/master' into HEAD 2017-10-09 09:48:38 -07:00
Andrew Waterman
986cbfb6b1 For Rockets without VM, widen vaddrBits to paddrBits 
This supports addressing a >39-bit physical address space.
 2017-10-08 01:21:47 -07:00
Andrew Waterman
a0e5a20b60 Don't route branch comparison result through ALU output mux 
This potentially mitigates a critical path, and makes the ALU usable
in processors that have dedicated branch comparators.
 2017-10-07 17:36:24 -07:00
Andrew Waterman
36c39d01e4 Factor out most of HasRocketTiles into HasTiles 2017-10-07 17:36:24 -07:00
Andrew Waterman
70a4127cb8 Factor out some of HaveRocketTiles into HaveTiles 2017-10-07 17:36:24 -07:00
Andrew Waterman
34e96c03b1 Move HCF to BaseTile 2017-10-07 17:36:24 -07:00
Andrew Waterman
71205b70cc Make RocketTileWrapper a BaseTile 2017-10-07 17:36:24 -07:00
Andrew Waterman
4645b61fd3 Decouple BaseTile from HasTileLinkMasterPort 2017-10-07 17:36:24 -07:00
Henry Styles
5498468743 FPU : simplify pipeline register generation in FMA 2017-10-05 15:18:19 -07:00
Henry Styles
7a46715cbc FPU : to assist retiming move upto first 2 register stages of into FMA 2017-10-05 15:18:04 -07:00