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riscv/rocket-chip
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5,168 Commits 1 Branch 0 Tags
71205b70cc56b9c07cea3d8d9ea5ebd50b01e9a6
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Author SHA1 Message Date
Richard Xia dd5934b6dc Bump riscv-tools to bump riscv-tests for mi-csr test fix and pull in stable binutils. 2017-08-08 16:29:26 -07:00
Richard Xia d62787357b Rename offchip-interrupts to external-interrupts. 2017-07-13 15:56:22 -07:00
Richard Xia 5b46350bc3 Make sure that DCache s2_xcpt data scratchpad case is assigned to after initial assignment. 2017-06-30 17:44:16 -07:00
Richard Xia 61c39da475 Check for rvc before declaring illegal instruction after an ebreak. 2017-06-16 10:49:36 -07:00
Richard Xia 4e3682f889 Bump chisel3 by just one commit to pull in gitignore for firrtl.jar. 2016-11-26 12:24:10 -08:00
Richard Xia bab504cc3f Add various granular and composable configs. 2016-11-18 11:30:07 -08:00
Richard Xia 6e5dd45f9a Bump riscv-tools to bump riscv-tests to pull in OpenOCD port randomization fix. 2016-11-16 11:33:15 -08:00
Richard Xia cc5b7d1eb6 Bump riscv-tools. 2016-10-26 11:40:49 -07:00
Richard Xia 183ae58704 Use a random port number for JTAG VPI. 2016-10-26 11:40:45 -07:00
Richard Xia 3fdf40c088 Change implicit argument to explicit. 2016-09-16 17:47:31 -07:00
Richard Xia 63f13ae7ce Merge remote-tracking branch 'origin/master' into rxia-testharness-refactor 2016-09-16 17:10:52 -07:00
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