riscv/rocket-chip
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Author SHA1 Message Date
Andrew Waterman 63f8ce36f6 Avoid VM exceptions in groundtest by setting Accessed bit 2017-03-09 16:48:28 -08:00
Andrew Waterman 4f8f05d635 Add performance counter facility 2017-03-09 13:58:50 -08:00
Andrew Waterman e57ee2692d bump tools 2017-03-09 13:58:40 -08:00
Andrew Waterman 33b6d48376 Fix haltnot reporting (previously always returned 0) 2017-03-09 13:58:40 -08:00
Andrew Waterman 24a2278fc4 Perform all illegal-instruction detection in ID stage 
This is simpler, reduces what would have become a critical path in
the commit stage, and will make it easier to support the mbadinst
CSR if it is implemented.
 2017-03-09 11:29:51 -08:00
Andrew Waterman 7668827741 Support unrolling the integer divider 2017-03-09 11:29:51 -08:00
Andrew Waterman 74d8d672bf Improve BTB critical path at slight accuracy cost 
Make entries fully associative on lower 14 bits only, not full address.
 2017-03-09 11:29:51 -08:00
Andrew Waterman 11c8857b5d Don't re-read I$ RAMs on stall 2017-03-09 11:29:51 -08:00
Andrew Waterman db0a02b78e WIP on priv-1.10 2017-03-09 11:29:51 -08:00
Andrew WatermanandAndrew Waterman 603b8af2eb Don't canonicalize 32-bit FP results in the various pipelines 
It's redundant with the new scheme, so just adds HW for no reason.
 2017-03-07 20:51:32 -08:00
Andrew WatermanandAndrew Waterman f505aba1ac Use sNaN value for flw, like other single-precision ops 2017-03-07 20:51:32 -08:00
Andrew WatermanandAndrew Waterman cc389bea90 Fix in-register representation of fdiv.s/fsqrt.s result 
We were zero-extending it, which is a double-precision zero in the recoded
format.  So, when spilled and reloaded with fsd/fld, the original value
was destroyed.  Instead, set the MSBs so that it represents sNaN.  When
spilled, the single-precision number will be preserved as the NaN payload.
 2017-03-07 20:51:32 -08:00
Andrew Waterman dfa61bc487 Standardize Data.holdUnless and SeqMem.readAndHold 
- Make API more idiomatic (x holdUnless y, instead of holdUnless(x, y))
- Add new SeqMem API, readAndHold, which corresponds to most common
  use of holdUnless
 2017-02-25 03:07:49 -08:00
Andrew WatermanandAndrew Waterman 8225676a86 For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaN 
See https://github.com/riscv/riscv-isa-sim/issues/76
 2017-02-02 11:55:08 -08:00
Andrew WatermanandAndrew Waterman 75edf42323 Set xPIE=1 on xRET 
We were setting xPIE=0 instead.  This is a benign bug, but still a bug.
 2017-02-02 11:55:08 -08:00
Andrew WatermanandHenry Cook f1cb06142e bump tools 2017-01-11 13:21:55 -08:00
Andrew WatermanandHenry Cook 71c4b000b3 Don't special-case power-of-2 replacement policy for BTB 
PLRU wasn't implemented correctly for the BTB, since it wasn't
increasing the priority on replacement, only on usage.  Regardless,
this should be a second-order effect, so using FIFO always is fine.
 2017-01-11 13:21:55 -08:00
Andrew WatermanandHenry Cook 5f3fb64ef0 Per ABI, only x1 and x5 should be treated as function returns 
We were doing so for x3 and x7, as well, which could reduce performance
for compilers that happen to perform indirect jumps via t2 (x7).
 2016-11-22 12:01:05 -08:00
Andrew WatermanandHoward Mao 8a7fc75b53 fix metadata race in blocking L1 DCache 2016-07-28 17:54:28 -07:00