Wesley W. Terpstra
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5b594ced29
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Plic: support 0 interrupts gracefully
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2016-11-18 18:07:44 -08:00 |
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Wesley W. Terpstra
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37a3c22639
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rocketchip: move from using cde to config
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2016-11-18 16:18:33 -08:00 |
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Wesley W. Terpstra
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a12fea51e8
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Plic: skip reserved interrupt in interrupt map printout
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2016-10-31 11:42:47 -07:00 |
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Wesley W. Terpstra
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ba529c3716
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rocketchip: use TileLink2 interrupts
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2016-10-31 11:42:47 -07:00 |
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Wesley W. Terpstra
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0cc00e7616
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regressions: test scratchpad
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2016-10-31 11:42:47 -07:00 |
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Wesley W. Terpstra
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d2e9fa8ec6
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Plic: remove path from ready to bits
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2016-10-31 11:42:47 -07:00 |
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Wesley W. Terpstra
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89139a9492
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Plic: split constants from variables used in config string
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2016-10-31 11:42:13 -07:00 |
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Wesley W. Terpstra
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b99662796d
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PLIC: converted to TL2
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2016-10-31 11:42:13 -07:00 |
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Albert Ou
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ad618fd55d
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plic: Fix bit extraction
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2016-10-06 18:05:03 -07:00 |
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Andrew Waterman
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b1c777c7a2
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Fix PLIC enable bit access for #ints >= tlDataBits
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2016-10-06 16:21:14 -07:00 |
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Andrew Waterman
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02a2439222
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Support a degenerate PLIC with no interrupts
Resolves #249
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2016-09-07 11:21:13 -07:00 |
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Howard Mao
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7b20609d4d
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reorganize moving non-submodule packages into src/main/scala
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2016-08-19 13:45:23 -07:00 |
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