This makes it possible to treat chained composition associatively.
x := y :=? z :=* a ...
It also makes it easy to chain multiple optional adapters:
node :=? (Seq(a, b) ++ c ++ d)
We had planned for a while to add an 'Overwrite' message which obtains
permissions without requiring retrieval of data. This is useful whenever
a master knows it will completely replace the contents of a cache block.
Instead of calling it Overwrite, we decided to split the Acquire type.
If you AcquirePerm, you MUST Release and ProbeAck with Data.
* CacheCork: an error Grant still says 'toT' even though it is transient
Grants with errors must be handled by a client as though no actual
permissions were obtained, so that two clients do not both end up believing
that they own a block which is only temporarily offline. However, the
Grant MESSAGE should still match the request; ie. if you did Acquire.NtoT,
the response must be Grant.toT, even though the 'error' bit signals that
the Grant actually grants no permissions.
This keeps the implementation of request-response tracking in interstitial
adapters and FSMs simple, consistent with the way multibeat errors must
include all their beats.
* Error: handle permissions properly
FlipRendering { implicit p => ... } now changes the render direction of edges.
diplomatic NodeImps can specify a default render flip using the new 'render' method.
We used to place Monitors at the point of the ':='.
This was problematic because the clock domain might be wrong.
Thus, we needed to shove Monitors a lot.
Furthermore, now that we have cross-module ':=', you might not even
have access to the wires at the point where ':=' is invoked.
If a multibeat response comes back, the source might be reused.
If response reordering has made the multibeat response invalid,
we need to remember this even if the valid bit is cleared on reuse.
When we first implemented TL, we thought this was helpful, because
it made WidthWidgets stateless in all cases. However, it put too
much burden on all other masters and slaves, none of which benefitted
from this signal. Furthermore, even with addr_lo, WidthWidgets were
information lossy because when they widen, they have no information
about what to fill in the new high bits of addr_lo.
- split the data based on the address, not the mask
(the first version of TileLink did not have low address bits)
- the dependency on addr_lo is now exposed and easy to replace
- errors are properly OR reduced
- registers latched only as needed (was previously a shift register)
- combines beats without inspecting address (removes addr_lo dependency)
Consider the following waveform for two 4-beat bursts:
---A----A------------
-------D-----DDD-DDDD
Under TL rules, the second A can use the same source as the first A,
because the source is released for reuse on the first response beat.
However, if we fragment the requests, it looks like this:
---3210-3210---------
-------3-----210-3210
... now we've broken the rules because 210 are twice inflight.
To solve this, we alternate an a.source bit every time D completes a txn.
* coreplex collapse: peripherals now in coreplex
* coreplex: better factoring of TLBusWrapper attachement points
* diplomacy: allow monitorless :*= and :=*
* rocket: don't connect monitors to tile tim slave ports
* rename chip package to system
* coreplex: only sbus has a splitter
* TLFragmenter: Continuing my spot battles on requires without explanatory strings
* pbus: toFixedWidthSingleBeatSlave
* tilelink: more verbose requires
* use the new system package for regression
* sbus: add more explicit FIFO attachment points
* delete leftover top-level utils
* cleanup ResetVector and RTC
