They fit in the same part of the address space as DRAM would be, and
are coherent (because they are not cacheable).
They are currently limited to single cores without DRAM. We intend
to lift both restrictions, probably when we add support for
heterogeneous tiles.
Initial cut
checkpoint which compiles and runs but there is some off-by-1 in the protocol
Debugging the clock crossing logic
checkpoint which works
Clean up the AsyncMailbox black box