This option reduces the number of wires that cross the clock boundary.
This can be a useful feature if the clock boundary coincides with
a voltage boundary, in which case the number of level shifters is reduced.
However, this introduces a path that crosses from sink->source->sink domain,
so the option is disabled by default.
If the other clock domain is much faster than ours, it's reset
might be shorter than a single cycle in our domain. In that case,
we need to catch the reset and extend it.
This reverts commit a84a961a39.
The changes to RegisterCrossing.scala were unneeded after application of this branch.
The name changes made to the AsyncQueue.scala are reapplied at the end of this branch.
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were
* The AsyncQueue and AsyncDecoupledCrossing from junctions.
* All of the code in rocket's util.scala
* The BlackBox asynchronous reset registers from uncore.tilelink2
* The implicit definitions from uncore.util
