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2021 Commits

Author SHA1 Message Date
Henry Cook 329a5c35d4 tilelink: unsafe cache cork discards outer d.sink 2017-10-11 00:30:51 -07:00
Henry Cook 1240cb275c coreplex: TilePortParams formatting 2017-10-11 00:29:11 -07:00
Henry Cook 1867a5b226 rocket: only cache when AcquireT is possible 2017-10-10 18:06:58 -07:00
Henry Cook 37406706b4 coreplex: move CacheCork in front of SBus 
Continue to not allow caches to cache ROMs.
Update TinyConfig and WithStatelessBridge.
 2017-10-10 16:24:32 -07:00
Henry Cook 8f5f80f958 coreplex: TileSlavePortParams inject adapters into PBus 2017-10-10 15:25:08 -07:00
Henry Cook 660355004e coreplex: TileMasterPortParams inject adapters into SBus 2017-10-10 15:02:50 -07:00
Henry Cook 9026646459 coreplex: first cut at using RocketCrossingParams 2017-10-10 12:02:04 -07:00
Wesley W. Terpstra d6766a8c68 RocketTile: make sure 'hartid' is available for traits (#1037) 2017-10-09 21:03:18 -07:00
Andrew Waterman 2c4009a138 Fix paddrBits < xLen && paddrBits == vaddrBits case 
Require and/or force vaddrBits to be bigger than paddrBits so there's
room to zero-extend a physical address by 1 bit, so that when the virtual
address is sign-extended, the sign is zero.
 2017-10-09 16:48:04 -07:00
Megan Wachs 0e6aa7ae9d Merge pull request #1024 from freechipsproject/jtag_coverage 
Add Coverage points for JTAG TAP
 2017-10-09 12:29:18 -07:00
Megan Wachs 0916cf1bdd JTAG Coverage: Correct jtag_reset case 2017-10-09 09:54:15 -07:00
Megan Wachs 9efe1c448e Merge remote-tracking branch 'origin/master' into HEAD 2017-10-09 09:48:38 -07:00
Andrew Waterman 986cbfb6b1 For Rockets without VM, widen vaddrBits to paddrBits 
This supports addressing a >39-bit physical address space.
 2017-10-08 01:21:47 -07:00
Andrew Waterman a0e5a20b60 Don't route branch comparison result through ALU output mux 
This potentially mitigates a critical path, and makes the ALU usable
in processors that have dedicated branch comparators.
 2017-10-07 17:36:24 -07:00
Andrew Waterman 36c39d01e4 Factor out most of HasRocketTiles into HasTiles 2017-10-07 17:36:24 -07:00
Andrew Waterman 70a4127cb8 Factor out some of HaveRocketTiles into HaveTiles 2017-10-07 17:36:24 -07:00
Andrew Waterman 34e96c03b1 Move HCF to BaseTile 2017-10-07 17:36:24 -07:00
Andrew Waterman 71205b70cc Make RocketTileWrapper a BaseTile 2017-10-07 17:36:24 -07:00
Andrew Waterman 4645b61fd3 Decouple BaseTile from HasTileLinkMasterPort 2017-10-07 17:36:24 -07:00
Henry Styles 5498468743 FPU : simplify pipeline register generation in FMA 2017-10-05 15:18:19 -07:00
Henry Styles 7a46715cbc FPU : to assist retiming move upto first 2 register stages of into FMA 2017-10-05 15:18:04 -07:00
Wesley W. Terpstra bd045a3b95 tilelink: split Acquire into Acquire{Block,Perm} (#1030) 
We had planned for a while to add an 'Overwrite' message which obtains
permissions without requiring retrieval of data. This is useful whenever
a master knows it will completely replace the contents of a cache block.

Instead of calling it Overwrite, we decided to split the Acquire type.

If you AcquirePerm, you MUST Release and ProbeAck with Data.
 2017-10-05 12:49:49 -07:00
Wei Song (宋威) 81b9ac42a3 add comments to diplomacy resource. (#913) 2017-10-05 12:45:56 -07:00
Henry Cook 8da7aabd51 tile: supply hartid from RocketTileParams 
make WithNCores partial configs override rather than append more tiles
 2017-10-05 00:31:53 -07:00
Henry Cook 45581e60f0 Revert "Merge pull request #1027 from freechipsproject/dont-touch-hartid" 
This reverts commit 5232a29d7d, reversing
changes made to a2dc13669a.
 2017-10-05 00:26:44 -07:00
Andrew Waterman 5a84564203 Merge pull request #1023 from freechipsproject/csr-cleanup 
Generalize CSR file to support simpler cores
 2017-10-04 14:04:59 -07:00
Andrew Waterman 32fda51a2c Get rid of paddrBits from SystemBus (#1029) 2017-10-04 12:11:37 -07:00
Andrew Waterman 7bcf28c585 Define fetchBytes in HasCoreParams, not Frontend 
It is more generally useful.
 2017-10-03 17:34:18 -07:00
Andrew Waterman 2786e42d99 Don't register interrupts in CSRFile 
They are usually registered outside the tile in a CDC.
 2017-10-03 17:34:18 -07:00
Andrew Waterman 5cfe070932 Add option to make misa read-only 2017-10-03 17:34:18 -07:00
Andrew Waterman 09468a272b Add option to remove basic counters (mcycle/minstret) 2017-10-03 17:34:18 -07:00
Andrew Waterman ab0821f25b Move microarchitecture-neutral params from Rocket to Core 
This makes some of the units more reusable.
 2017-10-03 17:34:18 -07:00
Andrew Waterman 190d5c50d9 Remove deprecated custom-CSR support 2017-10-03 17:34:18 -07:00
Henry Cook 5232a29d7d Merge pull request #1027 from freechipsproject/dont-touch-hartid 
Make use of the new DontTouch annotation
 2017-10-03 12:55:34 -07:00
Henry Cook d33737802a util: add DontTouch trait with dontTouchPorts method 2017-10-02 19:36:34 -07:00
Henry Cook aa3a18222c HellaCache: users like to peep resp.data and resp.addr 2017-10-02 19:36:30 -07:00
Henry Cook cedfb0e784 coreplex: dontTouch the rocket_tile_inputs wire 
which contains hartid.
 2017-10-02 19:36:10 -07:00
Wesley W. Terpstra a2dc13669a Error grants (#1025) 
* CacheCork: an error Grant still says 'toT' even though it is transient

Grants with errors must be handled by a client as though no actual
permissions were obtained, so that two clients do not both end up believing
that they own a block which is only temporarily offline. However, the
Grant MESSAGE should still match the request; ie. if you did Acquire.NtoT,
the response must be Grant.toT, even though the 'error' bit signals that
the Grant actually grants no permissions.

This keeps the implementation of request-response tracking in interstitial
adapters and FSMs simple, consistent with the way multibeat errors must
include all their beats.

* Error: handle permissions properly
 2017-10-02 14:49:25 -07:00
Megan Wachs 9c9cb68462 JTAG Coverage: Add reset coverage points 2017-10-02 11:08:13 -07:00
Megan Wachs a8ab06d572 JTAG: Add coverage points to the JTAG Tap 2017-10-02 11:08:13 -07:00
Jack Koenig 8891bf1b64 Bump chisel3 and firrtl, update plugin versions 
And update chisel3 code
 2017-09-29 15:44:27 -07:00
Henry Cook 547bdc2b5b diplomacy: standardize sram device resource naming (#1022) 2017-09-29 14:52:26 -07:00
Andrew Waterman 9137f54f59 Merge pull request #1020 from freechipsproject/fix-trace-insn 
Provide correct trace insn on interrupts when possible
 2017-09-27 18:47:24 -07:00
Andrew Waterman 9eaf50762e Don't report exceptions as valid instructions in the printed log 2017-09-27 16:29:42 -07:00
Wesley W. Terpstra 0a287df0f7 Merge remote-tracking branch 'origin/master' into auto-diplomacy-bundles 2017-09-27 16:28:10 -07:00
Andrew Waterman 31c5246446 Provide correct trace insn on interrupts when possible 2017-09-27 16:27:53 -07:00
Wesley W. Terpstra feae216f05 clint: output interrupts in the correct direction 2017-09-27 15:18:42 -07:00
Henry Cook 05112b49a3 Merge branch 'master' into tl-error 2017-09-27 14:50:17 -07:00
Henry Cook 652d57291c Merge pull request #1018 from freechipsproject/refine-trace-port 
Separate interrupt bit from cause field in trace bundle
 2017-09-27 14:46:27 -07:00
Wesley W. Terpstra 9307092d14 coreplex: draw the FrontBus at the bottom and SystemBus at the top 2017-09-27 14:20:39 -07:00