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riscv
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rocket-chip
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3 Commits
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Message
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Yunsup Lee
4c7c3f5bb2
add test generate for ZscaleTop
2015-07-14 16:26:28 -07:00
Henry Cook
302cd3e638
Added BuildZscale param for use in Top and makefrag generation
2015-07-13 15:46:42 -07:00
Yunsup Lee
09e29e8fe0
add zscale
...
only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
2015-07-07 20:38:47 -07:00