riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
4,945 Commits 1 Branch 0 Tags
1db4b3be9a694e1c648aaa92a7295aa9c3adec07
Commit Graph
3 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
Leway Colin 60c896b48c Typo: is should be if ? (#786) 
Typo: is should be if ?
 2017-06-07 10:40:13 -07:00
Leway Colin 1322a02637 Fixed Hasti can't handle N masters to one slave #571 (#576) 2017-03-13 20:36:53 -07:00
Leway Colin 87d909e996 Fix HastiTestSRAM can't R/W byte when HSIZE is 0 (#563) 2017-02-24 10:37:26 -08:00