4 Commits

Author	SHA1	Message	Date
Stephen Twigg	158cee08af	Adjust ordering of RoCCInstruction to reflect new ISA encoding. (Note: Fixes register op issues with AccumulatorExample but still slight issue with executing memory loads)	2013-09-22 03:18:06 -07:00
Andrew Waterman	f12bbc1e43	working RoCC AccumulatorExample	2013-09-14 22:34:53 -07:00
Andrew Waterman	a0cb711451	Start adding RoCC	2013-09-14 15:31:50 -07:00
Andrew Waterman	d053bdc89f	Remove Hwacha from Rocket ... Soon it will use the coprocessor interface.	2013-09-12 22:34:38 -07:00