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riscv/rocket-chip
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10472b4296a7d3a53439def85e2ddc07aa3d05f7
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Author SHA1 Message Date
Henry Styles 5498468743 FPU : simplify pipeline register generation in FMA 2017-10-05 15:18:19 -07:00
Henry Styles 7a46715cbc FPU : to assist retiming move upto first 2 register stages of into FMA 2017-10-05 15:18:04 -07:00
Henry StylesandWesley W. Terpstra f7330028cc Add optional frontbus for peripherals mastering into SBus. Switch FF and Buffer order on non-tile masters into SBus. Buffer non-L2 side of splitter 2017-08-30 14:22:49 -07:00
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