4 Commits

Author	SHA1	Message	Date
Yunsup Lee	02c08a156f	generate consts.vh from chisel source	2014-09-10 17:14:55 -07:00
Yunsup Lee	ddfd3ce968	further generalize fpga/vlsi builds	2014-09-08 00:21:57 -07:00
Yunsup Lee	763c57931b	fix problem introduced with verilog generation in vsim/fsim	2014-09-04 09:49:57 -07:00
Yunsup Lee	c03c09ec31	update for rocket-chip release	2014-08-31 20:26:55 -07:00