7 Commits

Author	SHA1	Message	Date
Howard Mao	f34843f1b9	fix assignment of incoherent vector	2016-09-04 10:12:16 -07:00
Yunsup Lee	a4c1942958	flatten Coreplex module hierarchy	2016-09-02 17:45:08 -07:00
Andrew Waterman	63679bb019	Add support for L1 data scratchpads instead of caches ... They fit in the same part of the address space as DRAM would be, and are coherent (because they are not cacheable). They are currently limited to single cores without DRAM. We intend to lift both restrictions, probably when we add support for heterogeneous tiles.	2016-09-02 16:22:07 -07:00
Megan Wachs	8163a6b597	Make it easier to override the 'placeholder' Real-Time-Clock, to allow more real-world applications	2016-09-02 11:11:40 -07:00
Andrew Waterman	f4524e4c91	Add PML for Boolean.option; use it	2016-08-31 13:43:04 -07:00
mwachs5	22ffe36258	Add a queue for timing QoR between L2->MMIO network (#217)	2016-08-19 22:51:49 -07:00
Howard Mao	7b20609d4d	reorganize moving non-submodule packages into src/main/scala	2016-08-19 13:45:23 -07:00