make sure TL -> NASTI converter acquire ready not dependent on valid
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1c135c1628
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@ -1421,33 +1421,43 @@ class NastiIOTileLinkIOConverter(implicit p: Parameters) extends TLModule()(p)
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require(tlDataBeats < (1 << nastiXLenBits), "Can't have that many beats")
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require(dstIdBits + tlClientXactIdBits < nastiXIdBits, "NastiIO converter is going truncate tags: " + dstIdBits + " + " + tlClientXactIdBits + " >= " + nastiXIdBits)
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io.tl.acquire.ready := Bool(false)
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io.nasti.b.ready := Bool(false)
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io.nasti.r.ready := Bool(false)
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io.nasti.ar.valid := Bool(false)
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io.nasti.aw.valid := Bool(false)
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io.nasti.w.valid := Bool(false)
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val dst_off = dstIdBits + tlClientXactIdBits
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val has_data = io.tl.acquire.bits.hasData()
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val is_write = io.tl.acquire.valid && has_data
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val is_subblock = io.tl.acquire.bits.isSubBlockType()
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val is_multibeat = io.tl.acquire.bits.hasMultibeatData()
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val (tl_cnt_out, tl_wrap_out) = Counter(
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io.tl.acquire.fire() && is_multibeat, tlDataBeats)
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val get_valid = io.tl.acquire.valid && !has_data
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val put_valid = io.tl.acquire.valid && has_data
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// Reorder queue saves extra information needed to send correct
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// grant back to TL client
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val roq = Module(new ReorderQueue(
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new NastiIOTileLinkIOConverterInfo,
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nastiRIdBits, tlMaxClientsPerPort))
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// For Get/GetBlock, make sure Reorder queue can accept new entry
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val get_helper = DecoupledHelper(
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get_valid,
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roq.io.enq.ready,
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io.nasti.ar.ready)
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val w_inflight = Reg(init = Bool(false))
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// For Put/PutBlock, make sure aw and w channel are both ready before
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// we send the first beat
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val aw_ready = w_inflight || io.nasti.aw.ready
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val put_helper = DecoupledHelper(
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put_valid,
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aw_ready,
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io.nasti.w.ready)
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val (nasti_cnt_out, nasti_wrap_out) = Counter(
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io.nasti.r.fire() && !roq.io.deq.data.subblock, tlDataBeats)
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roq.io.enq.valid := io.tl.acquire.fire() && !has_data
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roq.io.enq.valid := get_helper.fire(roq.io.enq.ready)
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roq.io.enq.bits.tag := io.nasti.ar.bits.id
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roq.io.enq.bits.data.byteOff := io.tl.acquire.bits.addr_byte()
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roq.io.enq.bits.data.subblock := is_subblock
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@ -1455,6 +1465,7 @@ class NastiIOTileLinkIOConverter(implicit p: Parameters) extends TLModule()(p)
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roq.io.deq.tag := io.nasti.r.bits.id
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// Decompose outgoing TL Acquires into Nasti address and data channels
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io.nasti.ar.valid := get_helper.fire(io.nasti.ar.ready)
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io.nasti.ar.bits := NastiReadAddressChannel(
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id = io.tl.acquire.bits.client_xact_id,
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addr = io.tl.acquire.bits.full_addr(),
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@ -1463,38 +1474,28 @@ class NastiIOTileLinkIOConverter(implicit p: Parameters) extends TLModule()(p)
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UInt(log2Ceil(tlDataBytes))),
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len = Mux(is_subblock, UInt(0), UInt(tlDataBeats - 1)))
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io.nasti.aw.valid := put_helper.fire(aw_ready, !w_inflight)
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io.nasti.aw.bits := NastiWriteAddressChannel(
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id = io.tl.acquire.bits.client_xact_id,
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addr = io.tl.acquire.bits.full_addr(),
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size = UInt(log2Ceil(tlDataBytes)),
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len = Mux(is_multibeat, UInt(tlDataBeats - 1), UInt(0)))
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io.nasti.w.valid := put_helper.fire(io.nasti.w.ready)
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io.nasti.w.bits := NastiWriteDataChannel(
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data = io.tl.acquire.bits.data,
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strb = io.tl.acquire.bits.wmask(),
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last = tl_wrap_out || (io.tl.acquire.fire() && is_subblock))
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val w_inflight = Reg(init = Bool(false))
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io.tl.acquire.ready := Mux(has_data,
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put_helper.fire(put_valid),
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get_helper.fire(get_valid))
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when (!w_inflight && io.tl.acquire.valid) {
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when (has_data) {
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// For Put/PutBlock, make sure aw and w channel are both ready before
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// we send the first beat
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io.tl.acquire.ready := io.nasti.aw.ready && io.nasti.w.ready
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io.nasti.aw.valid := io.nasti.w.ready
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io.nasti.w.valid := io.nasti.aw.ready
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// For Putblock, use a different state for the subsequent beats
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when (io.tl.acquire.ready && is_multibeat) { w_inflight := Bool(true) }
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} .otherwise {
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// For Get/GetBlock, make sure Reorder queue can accept new entry
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io.tl.acquire.ready := io.nasti.ar.ready && roq.io.enq.ready
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io.nasti.ar.valid := roq.io.enq.ready
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}
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when (!w_inflight && io.tl.acquire.fire() && is_multibeat) {
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w_inflight := Bool(true)
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}
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when (w_inflight) {
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io.nasti.w.valid := io.tl.acquire.valid
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io.tl.acquire.ready := io.nasti.w.ready
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when (tl_wrap_out) { w_inflight := Bool(false) }
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}
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