riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

fix WAW hazard handling

Browse Source
This commit is contained in:
Andrew Waterman
2012-01-02 00:25:11 -08:00
parent eb657dd250
commit ffe23a1ee8
6 changed files with 37 additions and 51 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
rocket/src/main/scala/nbdcache.scala
View File

@ -770,6 +770,7 @@ class HellaCache(lines: Int) extends Component {
io.cpu.req_rdy := flusher.io.req.ready && !(r_cpu_req_val_ && r_req_flush) && !pending_fence
io.cpu.resp_nack := r_cpu_req_val_ && !io.cpu.req_kill && nack
io.cpu.resp_val := (tag_hit && !nack_hit && r_req_read) || replayer.io.cpu_resp_val
io.cpu.resp_replay := replayer.io.cpu_resp_val
io.cpu.resp_miss := tag_miss && !nack_miss && r_req_read
io.cpu.resp_tag := Mux(replayer.io.cpu_resp_val, replayer.io.cpu_resp_tag, r_cpu_req_tag)
io.cpu.resp_data := loadgen.io.dout