riscv/rocket-chip
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fix WAW hazard handling

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This commit is contained in:
Andrew Waterman
2012-01-02 00:25:11 -08:00
parent eb657dd250
commit ffe23a1ee8
6 changed files with 37 additions and 51 deletions
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rocket/src/main/scala/dpath.scala
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@ -11,6 +11,7 @@ class ioDpathDmem extends Bundle()
val req_tag = UFix(CPU_TAG_BITS, 'output);
val req_data = Bits(64, 'output);
val resp_val = Bool('input);
val resp_replay = Bool('input);
val resp_tag = Bits(CPU_TAG_BITS, 'input);
val resp_data = Bits(64, 'input);
val resp_data_subword = Bits(64, 'input);