riscv/rocket-chip
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[rocket] only write badaddr on certain exceptions

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This commit is contained in:
Andrew Waterman 2016-07-29 15:18:39 -07:00
parent 0d3d9fca25
commit ffac86b041
2 changed files with 12 additions and 2 deletions
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8
rocket/src/main/scala/csr.scala
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@ -397,6 +397,10 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
val epc = ~(~io.pc | (coreInstBytes-1))
val pie = read_mstatus(reg_mstatus.prv)
val write_badaddr = cause isOneOf (Causes.breakpoint,
Causes.misaligned_load, Causes.misaligned_store, Causes.misaligned_fetch,
Causes.fault_load, Causes.fault_store, Causes.fault_fetch)
when (trapToDebug) {
reg_debug := true
reg_dpc := epc
@ -405,7 +409,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
}.elsewhen (delegate) {
reg_sepc := epc
reg_scause := cause
reg_sbadaddr := io.badaddr
when (write_badaddr) { reg_sbadaddr := io.badaddr }
reg_mstatus.spie := pie
reg_mstatus.spp := reg_mstatus.prv
reg_mstatus.sie := false
@ -413,7 +417,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
}.otherwise {
reg_mepc := epc
reg_mcause := cause
reg_mbadaddr := io.badaddr
when (write_badaddr) { reg_mbadaddr := io.badaddr }
reg_mstatus.mpie := pie
reg_mstatus.mpp := reg_mstatus.prv
reg_mstatus.mie := false

6
rocket/src/main/scala/util.scala
View File

@ -49,6 +49,12 @@ object Util {
def minUInt(first: UInt, rest: UInt*): UInt =
minUInt(first +: rest.toSeq)
implicit class UIntIsOneOf(val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).reduce(_||_)
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
}
import Util._