diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala
index 86090c2f..3214797d 100644
--- a/rocket/src/main/scala/csr.scala
+++ b/rocket/src/main/scala/csr.scala
@@ -397,6 +397,10 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
     val epc = ~(~io.pc | (coreInstBytes-1))
     val pie = read_mstatus(reg_mstatus.prv)
 
+    val write_badaddr = cause isOneOf (Causes.breakpoint,
+      Causes.misaligned_load, Causes.misaligned_store, Causes.misaligned_fetch,
+      Causes.fault_load, Causes.fault_store, Causes.fault_fetch)
+
     when (trapToDebug) {
       reg_debug := true
       reg_dpc := epc
@@ -405,7 +409,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
     }.elsewhen (delegate) {
       reg_sepc := epc
       reg_scause := cause
-      reg_sbadaddr := io.badaddr
+      when (write_badaddr) { reg_sbadaddr := io.badaddr }
       reg_mstatus.spie := pie
       reg_mstatus.spp := reg_mstatus.prv
       reg_mstatus.sie := false
@@ -413,7 +417,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
     }.otherwise {
       reg_mepc := epc
       reg_mcause := cause
-      reg_mbadaddr := io.badaddr
+      when (write_badaddr) { reg_mbadaddr := io.badaddr }
       reg_mstatus.mpie := pie
       reg_mstatus.mpp := reg_mstatus.prv
       reg_mstatus.mie := false
diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala
index 40a3c4a9..51c702f1 100644
--- a/rocket/src/main/scala/util.scala
+++ b/rocket/src/main/scala/util.scala
@@ -49,6 +49,12 @@ object Util {
 
   def minUInt(first: UInt, rest: UInt*): UInt =
     minUInt(first +: rest.toSeq)
+
+  implicit class UIntIsOneOf(val x: UInt) extends AnyVal {
+    def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).reduce(_||_)
+
+    def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
+  }
 }
 
 import Util._