hookup rocc interrupt and s bit

rocket/src/main/scala/ctrl.scala

@@ -745,4 +745,5 @@ class Control(implicit conf: RocketConfiguration) extends Module
 
   io.rocc.cmd.valid := wb_rocc_val
   io.rocc.exception := wb_reg_xcpt && sr.er
+  io.rocc.s := sr.s
 }

rocket/src/main/scala/dpath.scala

@@ -190,6 +190,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
   pcr.io.host <> io.host
   pcr.io <> io.ctrl
   pcr.io <> io.fpu
+  pcr.io.rocc <> io.rocc
   pcr.io.pc := wb_reg_pc
   io.ctrl.csr_replay := pcr.io.replay
 

rocket/src/main/scala/dpath_util.scala

@@ -108,6 +108,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
     val time = UInt(OUTPUT, conf.xprlen)
     val fcsr_rm = Bits(OUTPUT, FPConstants.RM_SZ)
     val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ)).flip
+    val rocc = new RoCCInterface().flip
   }
  
   val reg_epc = Reg(Bits(width = VADDR_BITS+1))
@@ -169,7 +170,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
 
   io.status := reg_status
   io.status.ip := Cat(r_irq_timer, reg_fromhost.orR,  r_irq_ipi,   Bool(false),
-                      Bool(false), Bool(false),      Bool(false), Bool(false))
+                      Bool(false), io.rocc.interrupt, Bool(false), Bool(false))
   io.fatc := wen && decoded_addr(CSRs.fatc)
   io.evec := Mux(io.exception, reg_evec.toSInt, reg_epc).toUInt
   io.ptbr := reg_ptbr

rocket/src/main/scala/rocc.scala

@@ -39,6 +39,7 @@ class RoCCInterface(implicit conf: RocketConfiguration) extends Bundle
   val resp = Decoupled(new RoCCResponse)
   val mem = new HellaCacheIO()(conf.dcache)
   val busy = Bool(OUTPUT)
+  val s = Bool(INPUT)
   val interrupt = Bool(OUTPUT)
   
   // These should be handled differently, eventually