riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

hookup rocc interrupt and s bit

Browse Source
This commit is contained in:
Yunsup Lee 2014-02-06 00:09:42 -08:00
parent ab4a3e937b
commit ff7cae29f7
4 changed files with 6 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
rocket/src/main/scala/ctrl.scala
View File

@ -745,4 +745,5 @@ class Control(implicit conf: RocketConfiguration) extends Module
io.rocc.cmd.valid := wb_rocc_val io.rocc.cmd.valid := wb_rocc_val
io.rocc.exception := wb_reg_xcpt && sr.er io.rocc.exception := wb_reg_xcpt && sr.er
io.rocc.s := sr.s
} }

1
rocket/src/main/scala/dpath.scala
View File

@ -190,6 +190,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
pcr.io.host <> io.host pcr.io.host <> io.host
pcr.io <> io.ctrl pcr.io <> io.ctrl
pcr.io <> io.fpu pcr.io <> io.fpu
pcr.io.rocc <> io.rocc
pcr.io.pc := wb_reg_pc pcr.io.pc := wb_reg_pc
io.ctrl.csr_replay := pcr.io.replay io.ctrl.csr_replay := pcr.io.replay

5
rocket/src/main/scala/dpath_util.scala
View File

@ -108,6 +108,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
val time = UInt(OUTPUT, conf.xprlen) val time = UInt(OUTPUT, conf.xprlen)
val fcsr_rm = Bits(OUTPUT, FPConstants.RM_SZ) val fcsr_rm = Bits(OUTPUT, FPConstants.RM_SZ)
val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ)).flip val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ)).flip
val rocc = new RoCCInterface().flip
} }
val reg_epc = Reg(Bits(width = VADDR_BITS+1)) val reg_epc = Reg(Bits(width = VADDR_BITS+1))
@ -168,8 +169,8 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
val wdata = Mux(cpu_req_valid, io.rw.wdata, host_pcr_bits.data) val wdata = Mux(cpu_req_valid, io.rw.wdata, host_pcr_bits.data)
io.status := reg_status io.status := reg_status
io.status.ip := Cat(r_irq_timer, reg_fromhost.orR, r_irq_ipi, Bool(false), io.status.ip := Cat(r_irq_timer, reg_fromhost.orR, r_irq_ipi, Bool(false),
Bool(false), Bool(false), Bool(false), Bool(false)) Bool(false), io.rocc.interrupt, Bool(false), Bool(false))
io.fatc := wen && decoded_addr(CSRs.fatc) io.fatc := wen && decoded_addr(CSRs.fatc)
io.evec := Mux(io.exception, reg_evec.toSInt, reg_epc).toUInt io.evec := Mux(io.exception, reg_evec.toSInt, reg_epc).toUInt
io.ptbr := reg_ptbr io.ptbr := reg_ptbr

1
rocket/src/main/scala/rocc.scala
View File

@ -39,6 +39,7 @@ class RoCCInterface(implicit conf: RocketConfiguration) extends Bundle
val resp = Decoupled(new RoCCResponse) val resp = Decoupled(new RoCCResponse)
val mem = new HellaCacheIO()(conf.dcache) val mem = new HellaCacheIO()(conf.dcache)
val busy = Bool(OUTPUT) val busy = Bool(OUTPUT)
val s = Bool(INPUT)
val interrupt = Bool(OUTPUT) val interrupt = Bool(OUTPUT)
// These should be handled differently, eventually // These should be handled differently, eventually