riscv/rocket-chip
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clint: output interrupts in the correct direction

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This commit is contained in:
Wesley W. Terpstra 2017-09-27 15:18:42 -07:00
parent 9307092d14
commit feae216f05
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/devices/tilelink/Clint.scala
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@ -68,8 +68,8 @@ class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) exte
val timecmp = Seq.fill(nTiles) { Seq.fill(timeWidth/regWidth)(Reg(UInt(width = regWidth))) }
val ipi = Seq.fill(nTiles) { RegInit(UInt(0, width = 1)) }
val (intnode_in, _) = intnode.in.unzip
intnode_in.zipWithIndex.foreach { case (int, i) =>
val (intnode_out, _) = intnode.out.unzip
intnode_out.zipWithIndex.foreach { case (int, i) =>
int(0) := ShiftRegister(ipi(i)(0), params.intStages) // msip
int(1) := ShiftRegister(time.asUInt >= timecmp(i).asUInt, params.intStages) // mtip
}