From feae216f05eb17292525ca28fc402dd2b0518294 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 27 Sep 2017 15:18:42 -0700 Subject: [PATCH] clint: output interrupts in the correct direction --- src/main/scala/devices/tilelink/Clint.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/devices/tilelink/Clint.scala b/src/main/scala/devices/tilelink/Clint.scala index 1419c137..5083ba9b 100644 --- a/src/main/scala/devices/tilelink/Clint.scala +++ b/src/main/scala/devices/tilelink/Clint.scala @@ -68,8 +68,8 @@ class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) exte val timecmp = Seq.fill(nTiles) { Seq.fill(timeWidth/regWidth)(Reg(UInt(width = regWidth))) } val ipi = Seq.fill(nTiles) { RegInit(UInt(0, width = 1)) } - val (intnode_in, _) = intnode.in.unzip - intnode_in.zipWithIndex.foreach { case (int, i) => + val (intnode_out, _) = intnode.out.unzip + intnode_out.zipWithIndex.foreach { case (int, i) => int(0) := ShiftRegister(ipi(i)(0), params.intStages) // msip int(1) := ShiftRegister(time.asUInt >= timecmp(i).asUInt, params.intStages) // mtip }