riscv/rocket-chip
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PeripheryBus: automatically disappear when not used

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This commit is contained in:
Wesley W. Terpstra 2017-11-30 16:34:46 -08:00
parent 93c8010aca
commit fe8d557751
2 changed files with 3 additions and 3 deletions
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4
src/main/scala/coreplex/PeripheryBus.scala
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@ -33,7 +33,7 @@ class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends T
val fromSystemBus: TLInwardNode = { val fromSystemBus: TLInwardNode = {
val atomics = LazyModule(new TLAtomicAutomata(arithmetic = params.arithmetic)) val atomics = LazyModule(new TLAtomicAutomata(arithmetic = params.arithmetic))
inwardBufNode := atomics.node xbar.node :*= TLBuffer(params.masterBuffering) :*= atomics.node
} }
def toTile(name: Option[String] = None)(gen: Parameters => TLInwardNode) { def toTile(name: Option[String] = None)(gen: Parameters => TLInwardNode) {
@ -59,5 +59,5 @@ trait HasPeripheryBus extends HasSystemBus {
val pbus = LazyModule(new PeripheryBus(pbusParams)) val pbus = LazyModule(new PeripheryBus(pbusParams))
// The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL // The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL
pbus.fromSystemBus := sbus.toPeripheryBus() pbus.fromSystemBus :*= sbus.toPeripheryBus()
} }

2
src/main/scala/coreplex/SystemBus.scala
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@ -39,7 +39,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
def toSplitSlaves: TLOutwardNode = outwardSplitNode def toSplitSlaves: TLOutwardNode = outwardSplitNode
def toPeripheryBus(addBuffers: Int = 0): TLOutwardNode = { def toPeripheryBus(addBuffers: Int = 0): TLOutwardNode = {
TLBuffer.chain(addBuffers).foldRight(pbus_fixer.node:TLOutwardNode)(_ := _) TLBuffer.chain(addBuffers).foldRight(pbus_fixer.node:TLOutwardNode)(_ :*= _)
} }
val toMemoryBus: TLOutwardNode = outwardNode val toMemoryBus: TLOutwardNode = outwardNode